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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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908 EMIT(0xD1); | 908 EMIT(0xD1); |
909 EMIT(0xD8 | dst.code()); | 909 EMIT(0xD8 | dst.code()); |
910 } else { | 910 } else { |
911 EMIT(0xC1); | 911 EMIT(0xC1); |
912 EMIT(0xD8 | dst.code()); | 912 EMIT(0xD8 | dst.code()); |
913 EMIT(imm8); | 913 EMIT(imm8); |
914 } | 914 } |
915 } | 915 } |
916 | 916 |
917 | 917 |
918 void Assembler::ror(Register dst, uint8_t imm8) { | 918 void Assembler::ror(const Operand& dst, uint8_t imm8) { |
919 EnsureSpace ensure_space(this); | 919 EnsureSpace ensure_space(this); |
920 DCHECK(is_uint5(imm8)); // illegal shift count | 920 DCHECK(is_uint5(imm8)); // illegal shift count |
921 if (imm8 == 1) { | 921 if (imm8 == 1) { |
922 EMIT(0xD1); | 922 EMIT(0xD1); |
923 EMIT(0xC8 | dst.code()); | 923 emit_operand(ecx, dst); |
924 } else { | 924 } else { |
925 EMIT(0xC1); | 925 EMIT(0xC1); |
926 EMIT(0xC8 | dst.code()); | 926 emit_operand(ecx, dst); |
927 EMIT(imm8); | 927 EMIT(imm8); |
928 } | 928 } |
929 } | 929 } |
930 | 930 |
931 | 931 |
932 void Assembler::ror_cl(Register dst) { | 932 void Assembler::ror_cl(const Operand& dst) { |
933 EnsureSpace ensure_space(this); | 933 EnsureSpace ensure_space(this); |
934 EMIT(0xD3); | 934 EMIT(0xD3); |
935 EMIT(0xC8 | dst.code()); | 935 emit_operand(ecx, dst); |
936 } | 936 } |
937 | 937 |
938 | 938 |
939 void Assembler::sar(const Operand& dst, uint8_t imm8) { | 939 void Assembler::sar(const Operand& dst, uint8_t imm8) { |
940 EnsureSpace ensure_space(this); | 940 EnsureSpace ensure_space(this); |
941 DCHECK(is_uint5(imm8)); // illegal shift count | 941 DCHECK(is_uint5(imm8)); // illegal shift count |
942 if (imm8 == 1) { | 942 if (imm8 == 1) { |
943 EMIT(0xD1); | 943 EMIT(0xD1); |
944 emit_operand(edi, dst); | 944 emit_operand(edi, dst); |
945 } else { | 945 } else { |
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2089 fprintf(coverage_log, "%s\n", file_line); | 2089 fprintf(coverage_log, "%s\n", file_line); |
2090 fflush(coverage_log); | 2090 fflush(coverage_log); |
2091 } | 2091 } |
2092 } | 2092 } |
2093 | 2093 |
2094 #endif | 2094 #endif |
2095 | 2095 |
2096 } } // namespace v8::internal | 2096 } } // namespace v8::internal |
2097 | 2097 |
2098 #endif // V8_TARGET_ARCH_X87 | 2098 #endif // V8_TARGET_ARCH_X87 |
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