Index: tests/fixedfeaturecpu/nacl.scons |
diff --git a/tests/fixedfeaturecpu/nacl.scons b/tests/fixedfeaturecpu/nacl.scons |
index fbe82b962146bf7612c223a3be05880150993ad7..2b2808611229e42a6c83ba12b9e277964dfdb2d9 100644 |
--- a/tests/fixedfeaturecpu/nacl.scons |
+++ b/tests/fixedfeaturecpu/nacl.scons |
@@ -37,7 +37,6 @@ is_validation_broken = env.IsRunningUnderValgrind() |
# problems. |
if env.Bit('tests_use_irt'): |
if (env.Bit('target_x86_64') and |
- env.Bit('validator_ragel') and |
not env.Bit('nacl_glibc')): |
# R-DFA ignores LM bit and assumes it's always enabled |
expect_null_Z_status=0 |
@@ -45,7 +44,6 @@ if env.Bit('tests_use_irt'): |
else: |
# 32-bit irt newlib: requeres MMX(prefetchnta),CLFLUSH/FXSR(sfence) |
# 64-bit irt newlib: requires LM(cltq),MMX(prefetchnta),CLFLUSH/FXSR(sfence) |
- # prefetchnta and sfence are classified incorrectly in the old validator |
expect_null_Z_status=1 |
expect_sse_Z_status=1 |
expect_x87_Z_status=1 |
@@ -67,15 +65,9 @@ else: |
expect_sse_Z_status=1 |
expect_x87_Z_status=1 |
elif env.Bit('target_x86_64'): |
- if env.Bit('validator_ragel'): |
- # R-DFA ignores LM bit and assumes it's always enabled |
- expect_null_Z_status=0 |
- expect_sse_Z_status=0 |
- else: |
- # 64-bit newlib: requires LM(cltq), MMX(prefetchnta), CLFLUSH/FXSR(sfence) |
- # prefetchnta and sfence are classified incorrectly in the old validator |
- expect_null_Z_status=1 |
- expect_sse_Z_status=1 |
+ # R-DFA ignores LM bit and assumes it's always enabled |
+ expect_null_Z_status=0 |
+ expect_sse_Z_status=0 |
expect_x87_Z_status=1 |
test_suites = ['small_tests', 'sel_ldr_tests', 'validator_tests'] |