| Index: third_party/tcmalloc/chromium/src/base/atomicops-internals-x86.h
|
| diff --git a/third_party/tcmalloc/chromium/src/base/atomicops-internals-x86.h b/third_party/tcmalloc/chromium/src/base/atomicops-internals-x86.h
|
| index c34aa5c08fc0885380b4f60ce5ddd9ebed55204f..8d3f335d0f24a286376be195f023df4dd7c1803a 100644
|
| --- a/third_party/tcmalloc/chromium/src/base/atomicops-internals-x86.h
|
| +++ b/third_party/tcmalloc/chromium/src/base/atomicops-internals-x86.h
|
| @@ -46,19 +46,6 @@ typedef int32_t Atomic32;
|
| // already matches Atomic32 or Atomic64, depending on the platform.
|
|
|
|
|
| -// This struct is not part of the public API of this module; clients may not
|
| -// use it.
|
| -// Features of this x86. Values may not be correct before main() is run,
|
| -// but are set conservatively.
|
| -struct AtomicOps_x86CPUFeatureStruct {
|
| - bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
|
| - // after acquire compare-and-swap.
|
| - bool has_sse2; // Processor has SSE2.
|
| - bool has_cmpxchg16b; // Processor supports cmpxchg16b instruction.
|
| -};
|
| -extern struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures;
|
| -
|
| -
|
| #define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
|
|
|
|
|
| @@ -106,9 +93,6 @@ inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
|
| : "+r" (temp), "+m" (*ptr)
|
| : : "memory");
|
| // temp now holds the old value of *ptr
|
| - if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
|
| - __asm__ __volatile__("lfence" : : : "memory");
|
| - }
|
| return temp + increment;
|
| }
|
|
|
| @@ -116,9 +100,6 @@ inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
|
| Atomic32 old_value,
|
| Atomic32 new_value) {
|
| Atomic32 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
|
| - if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
|
| - __asm__ __volatile__("lfence" : : : "memory");
|
| - }
|
| return x;
|
| }
|
|
|
| @@ -148,22 +129,12 @@ inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
|
| #else
|
|
|
| inline void MemoryBarrier() {
|
| - if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
|
| - __asm__ __volatile__("mfence" : : : "memory");
|
| - } else { // mfence is faster but not present on PIII
|
| - Atomic32 x = 0;
|
| - NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII
|
| - }
|
| + __asm__ __volatile__("mfence" : : : "memory");
|
| }
|
|
|
| inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
|
| - if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
|
| - *ptr = value;
|
| - __asm__ __volatile__("mfence" : : : "memory");
|
| - } else {
|
| - NoBarrier_AtomicExchange(ptr, value);
|
| - // acts as a barrier on PIII
|
| - }
|
| + *ptr = value;
|
| + __asm__ __volatile__("mfence" : : : "memory");
|
| }
|
| #endif
|
|
|
| @@ -230,9 +201,6 @@ inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
|
| : "+r" (temp), "+m" (*ptr)
|
| : : "memory");
|
| // temp now contains the previous value of *ptr
|
| - if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
|
| - __asm__ __volatile__("lfence" : : : "memory");
|
| - }
|
| return temp + increment;
|
| }
|
|
|
| @@ -349,9 +317,6 @@ inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
|
| inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
|
| Atomic64 increment) {
|
| Atomic64 new_val = NoBarrier_AtomicIncrement(ptr, increment);
|
| - if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
|
| - __asm__ __volatile__("lfence" : : : "memory");
|
| - }
|
| return new_val;
|
| }
|
|
|
| @@ -408,9 +373,6 @@ inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
|
| Atomic64 old_value,
|
| Atomic64 new_value) {
|
| Atomic64 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
|
| - if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
|
| - __asm__ __volatile__("lfence" : : : "memory");
|
| - }
|
| return x;
|
| }
|
|
|
|
|