OLD | NEW |
1 // Copyright (c) 2006-2008 The Chromium Authors. All rights reserved. | 1 // Copyright (c) 2006-2008 The Chromium Authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // This module gets enough CPU information to optimize the | 5 // This module gets enough CPU information to optimize the |
6 // atomicops module on x86. | 6 // atomicops module on x86. |
7 | 7 |
8 #include <stdint.h> | 8 #include <stdint.h> |
9 #include <string.h> | 9 #include <string.h> |
10 | 10 |
11 #include "base/atomicops.h" | 11 #include "base/atomicops.h" |
12 | 12 |
13 // This file only makes sense with atomicops_internals_x86_gcc.h -- it | |
14 // depends on structs that are defined in that file. If atomicops.h | |
15 // doesn't sub-include that file, then we aren't needed, and shouldn't | |
16 // try to do anything. | |
17 #ifdef BASE_ATOMICOPS_INTERNALS_X86_GCC_H_ | |
18 | |
19 // Inline cpuid instruction. In PIC compilations, %ebx contains the address | 13 // Inline cpuid instruction. In PIC compilations, %ebx contains the address |
20 // of the global offset table. To avoid breaking such executables, this code | 14 // of the global offset table. To avoid breaking such executables, this code |
21 // must preserve that register's value across cpuid instructions. | 15 // must preserve that register's value across cpuid instructions. |
| 16 // |
| 17 // The include guards are the same as in atomicops.h. |
22 #if defined(__i386__) | 18 #if defined(__i386__) |
23 #define cpuid(a, b, c, d, inp) \ | 19 #define cpuid(a, b, c, d, inp) \ |
24 asm("mov %%ebx, %%edi\n" \ | 20 asm("mov %%ebx, %%edi\n" \ |
25 "cpuid\n" \ | 21 "cpuid\n" \ |
26 "xchg %%edi, %%ebx\n" \ | 22 "xchg %%edi, %%ebx\n" \ |
27 : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) | 23 : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) |
28 #elif defined(__x86_64__) | 24 #elif defined(__x86_64__) |
29 #define cpuid(a, b, c, d, inp) \ | 25 #define cpuid(a, b, c, d, inp) \ |
30 asm("mov %%rbx, %%rdi\n" \ | 26 asm("mov %%rbx, %%rdi\n" \ |
31 "cpuid\n" \ | 27 "cpuid\n" \ |
32 "xchg %%rdi, %%rbx\n" \ | 28 "xchg %%rdi, %%rbx\n" \ |
33 : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) | 29 : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) |
34 #endif | 30 #endif |
35 | 31 |
36 #if defined(cpuid) // initialize the struct only on x86 | 32 #if defined(cpuid) // initialize the struct only on x86 |
37 | 33 |
38 // Set the flags so that code will run correctly and conservatively, so even | 34 // Set the flags so that code will run correctly and conservatively, so even |
39 // if we haven't been initialized yet, we're probably single threaded, and our | 35 // if we haven't been initialized yet, we're probably single threaded, and our |
40 // default values should hopefully be pretty safe. | 36 // default values should hopefully be pretty safe. |
41 struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = { | 37 struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = { |
42 false, // bug can't exist before process spawns multiple threads | 38 false, // bug can't exist before process spawns multiple threads |
| 39 false, // Chrome requires SSE2, but for transition assume not and initialize |
| 40 // this properly. |
| 41 false, // cmpxchg16b isn't present on early AMD64 CPUs. |
43 }; | 42 }; |
44 | 43 |
45 namespace { | 44 namespace { |
46 | 45 |
47 // Initialize the AtomicOps_Internalx86CPUFeatures struct. | 46 // Initialize the AtomicOps_Internalx86CPUFeatures struct. |
48 void AtomicOps_Internalx86CPUFeaturesInit() { | 47 void AtomicOps_Internalx86CPUFeaturesInit() { |
49 uint32_t eax; | 48 uint32_t eax; |
50 uint32_t ebx; | 49 uint32_t ebx; |
51 uint32_t ecx; | 50 uint32_t ecx; |
52 uint32_t edx; | 51 uint32_t edx; |
(...skipping 21 matching lines...) Expand all Loading... |
74 // non-locked read-modify-write instruction. Rev F has this bug in | 73 // non-locked read-modify-write instruction. Rev F has this bug in |
75 // pre-release versions, but not in versions released to customers, | 74 // pre-release versions, but not in versions released to customers, |
76 // so we test only for Rev E, which is family 15, model 32..63 inclusive. | 75 // so we test only for Rev E, which is family 15, model 32..63 inclusive. |
77 if (strcmp(vendor, "AuthenticAMD") == 0 && // AMD | 76 if (strcmp(vendor, "AuthenticAMD") == 0 && // AMD |
78 family == 15 && | 77 family == 15 && |
79 32 <= model && model <= 63) { | 78 32 <= model && model <= 63) { |
80 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true; | 79 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true; |
81 } else { | 80 } else { |
82 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false; | 81 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false; |
83 } | 82 } |
| 83 |
| 84 // edx bit 26 is SSE2 which we use to tell use whether we can use mfence |
| 85 AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1); |
| 86 |
| 87 // ecx bit 13 indicates whether the cmpxchg16b instruction is supported |
| 88 AtomicOps_Internalx86CPUFeatures.has_cmpxchg16b = ((ecx >> 13) & 1); |
84 } | 89 } |
85 | 90 |
86 class AtomicOpsx86Initializer { | 91 class AtomicOpsx86Initializer { |
87 public: | 92 public: |
88 AtomicOpsx86Initializer() { | 93 AtomicOpsx86Initializer() { |
89 AtomicOps_Internalx86CPUFeaturesInit(); | 94 AtomicOps_Internalx86CPUFeaturesInit(); |
90 } | 95 } |
91 }; | 96 }; |
92 | 97 |
93 // A global to get use initialized on startup via static initialization :/ | 98 // A global to get use initialized on startup via static initialization :/ |
94 AtomicOpsx86Initializer g_initer; | 99 AtomicOpsx86Initializer g_initer; |
95 | 100 |
96 } // namespace | 101 } // namespace |
97 | 102 |
98 #endif // if x86 | 103 #endif // if x86 |
99 | |
100 #endif // ifdef BASE_ATOMICOPS_INTERNALS_X86_GCC_H_ | |
OLD | NEW |