Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(897)

Unified Diff: runtime/vm/assembler_arm64.h

Issue 630093004: Fix 32-bit and 64-bit carry out calculation in arm64 simulator. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years, 2 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View side-by-side diff with in-line comments
Download patch
« no previous file with comments | « no previous file | runtime/vm/assembler_arm64_test.cc » ('j') | no next file with comments »
Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
Index: runtime/vm/assembler_arm64.h
===================================================================
--- runtime/vm/assembler_arm64.h (revision 40988)
+++ runtime/vm/assembler_arm64.h (working copy)
@@ -541,6 +541,9 @@
void addw(Register rd, Register rn, Operand o) {
AddSubHelper(kWord, false, false, rd, rn, o);
}
+ void addsw(Register rd, Register rn, Operand o) {
+ AddSubHelper(kWord, true, false, rd, rn, o);
+ }
void sub(Register rd, Register rn, Operand o) {
AddSubHelper(kDoubleWord, false, true, rd, rn, o);
}
@@ -547,7 +550,39 @@
void subs(Register rd, Register rn, Operand o) {
AddSubHelper(kDoubleWord, true, true, rd, rn, o);
}
+ void subw(Register rd, Register rn, Operand o) {
+ AddSubHelper(kWord, false, true, rd, rn, o);
+ }
+ void subsw(Register rd, Register rn, Operand o) {
+ AddSubHelper(kWord, true, true, rd, rn, o);
+ }
+ // Addition and subtraction with carry.
+ void adc(Register rd, Register rn, Register rm) {
+ AddSubWithCarryHelper(kDoubleWord, false, false, rd, rn, rm);
+ }
+ void adcs(Register rd, Register rn, Register rm) {
+ AddSubWithCarryHelper(kDoubleWord, true, false, rd, rn, rm);
+ }
+ void adcw(Register rd, Register rn, Register rm) {
+ AddSubWithCarryHelper(kWord, false, false, rd, rn, rm);
+ }
+ void adcsw(Register rd, Register rn, Register rm) {
+ AddSubWithCarryHelper(kWord, true, false, rd, rn, rm);
+ }
+ void sbc(Register rd, Register rn, Register rm) {
+ AddSubWithCarryHelper(kDoubleWord, false, true, rd, rn, rm);
+ }
+ void sbcs(Register rd, Register rn, Register rm) {
+ AddSubWithCarryHelper(kDoubleWord, true, true, rd, rn, rm);
+ }
+ void sbcw(Register rd, Register rn, Register rm) {
+ AddSubWithCarryHelper(kWord, false, true, rd, rn, rm);
+ }
+ void sbcsw(Register rd, Register rn, Register rm) {
+ AddSubWithCarryHelper(kWord, true, true, rd, rn, rm);
+ }
+
// PC relative immediate add. imm is in bytes.
void adr(Register rd, const Immediate& imm) {
EmitPCRelOp(ADR, rd, imm);
@@ -1427,6 +1462,24 @@
}
}
+ void AddSubWithCarryHelper(OperandSize sz, bool set_flags, bool subtract,
+ Register rd, Register rn, Register rm) {
+ ASSERT((rd != R31) && (rn != R31) && (rm != R31));
+ ASSERT((rd != CSP) && (rn != CSP) && (rm != CSP));
+ const Register crd = ConcreteRegister(rd);
+ const Register crn = ConcreteRegister(rn);
+ const Register crm = ConcreteRegister(rm);
+ const int32_t size = (sz == kDoubleWord) ? B31 : 0;
+ const int32_t s = set_flags ? B29 : 0;
+ const int32_t op = subtract ? SBC : ADC;
+ const int32_t encoding =
+ op | size | s |
+ (static_cast<int32_t>(crd) << kRdShift) |
+ (static_cast<int32_t>(crn) << kRnShift) |
+ (static_cast<int32_t>(crm) << kRmShift);
+ Emit(encoding);
+ }
+
void EmitAddSubImmOp(AddSubImmOp op, Register rd, Register rn,
Operand o, OperandSize sz, bool set_flags) {
ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
« no previous file with comments | « no previous file | runtime/vm/assembler_arm64_test.cc » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698