Fix 32-bit and 64-bit carry out calculation in arm64 simulator.

runtime/vm/disassembler_arm64.cc

Index: runtime/vm/disassembler_arm64.cc
===================================================================
--- runtime/vm/disassembler_arm64.cc	(revision 40955)
+++ runtime/vm/disassembler_arm64.cc	(working copy)
@@ -914,6 +914,23 @@
 }
 
 
+void ARM64Decoder::DecodeAddSubWithCarry(Instr* instr) {
+  switch (instr->Bit(30)) {
+    case 0: {
+      Format(instr, "adc'sf's 'rd, 'rn, 'rm");
+      break;
+    }
+    case 1: {
+      Format(instr, "sbc'sf's 'rd, 'rn, 'rm");
+      break;
+    }
+    default:
+      UNREACHABLE();
+      break;
+  }
+}
+
+
 void ARM64Decoder::DecodeLogicalShift(Instr* instr) {
   const int op = (instr->Bits(29, 2) << 1) | instr->Bit(21);
   switch (op) {
@@ -1019,6 +1036,8 @@
 void ARM64Decoder::DecodeDPRegister(Instr* instr) {
   if (instr->IsAddSubShiftExtOp()) {
     DecodeAddSubShiftExt(instr);
+  } else if (instr->IsAddSubWithCarryOp()) {
+    DecodeAddSubWithCarry(instr);
   } else if (instr->IsLogicalShiftOp()) {
     DecodeLogicalShift(instr);
   } else if (instr->IsMiscDP2SourceOp()) {