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Side by Side Diff: runtime/vm/disassembler_arm64.cc

Issue 630093004: Fix 32-bit and 64-bit carry out calculation in arm64 simulator. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years, 2 months ago
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1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/disassembler.h" 5 #include "vm/disassembler.h"
6 6
7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM64. 7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM64.
8 #if defined(TARGET_ARCH_ARM64) 8 #if defined(TARGET_ARCH_ARM64)
9 #include "platform/assert.h" 9 #include "platform/assert.h"
10 10
(...skipping 896 matching lines...) Expand 10 before | Expand all | Expand 10 after
907 } 907 }
908 break; 908 break;
909 } 909 }
910 default: 910 default:
911 UNREACHABLE(); 911 UNREACHABLE();
912 break; 912 break;
913 } 913 }
914 } 914 }
915 915
916 916
917 void ARM64Decoder::DecodeAddSubWithCarry(Instr* instr) {
918 switch (instr->Bit(30)) {
919 case 0: {
920 Format(instr, "adc'sf's 'rd, 'rn, 'rm");
921 break;
922 }
923 case 1: {
924 Format(instr, "sbc'sf's 'rd, 'rn, 'rm");
925 break;
926 }
927 default:
928 UNREACHABLE();
929 break;
930 }
931 }
932
933
917 void ARM64Decoder::DecodeLogicalShift(Instr* instr) { 934 void ARM64Decoder::DecodeLogicalShift(Instr* instr) {
918 const int op = (instr->Bits(29, 2) << 1) | instr->Bit(21); 935 const int op = (instr->Bits(29, 2) << 1) | instr->Bit(21);
919 switch (op) { 936 switch (op) {
920 case 0: 937 case 0:
921 Format(instr, "and'sf 'rd, 'rn, 'shift_op"); 938 Format(instr, "and'sf 'rd, 'rn, 'shift_op");
922 break; 939 break;
923 case 1: 940 case 1:
924 Format(instr, "bic'sf 'rd, 'rn, 'shift_op"); 941 Format(instr, "bic'sf 'rd, 'rn, 'shift_op");
925 break; 942 break;
926 case 2: { 943 case 2: {
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1012 Format(instr, "csinv'sf'cond 'rd, 'rn, 'rm"); 1029 Format(instr, "csinv'sf'cond 'rd, 'rn, 'rm");
1013 } else { 1030 } else {
1014 Unknown(instr); 1031 Unknown(instr);
1015 } 1032 }
1016 } 1033 }
1017 1034
1018 1035
1019 void ARM64Decoder::DecodeDPRegister(Instr* instr) { 1036 void ARM64Decoder::DecodeDPRegister(Instr* instr) {
1020 if (instr->IsAddSubShiftExtOp()) { 1037 if (instr->IsAddSubShiftExtOp()) {
1021 DecodeAddSubShiftExt(instr); 1038 DecodeAddSubShiftExt(instr);
1039 } else if (instr->IsAddSubWithCarryOp()) {
1040 DecodeAddSubWithCarry(instr);
1022 } else if (instr->IsLogicalShiftOp()) { 1041 } else if (instr->IsLogicalShiftOp()) {
1023 DecodeLogicalShift(instr); 1042 DecodeLogicalShift(instr);
1024 } else if (instr->IsMiscDP2SourceOp()) { 1043 } else if (instr->IsMiscDP2SourceOp()) {
1025 DecodeMiscDP2Source(instr); 1044 DecodeMiscDP2Source(instr);
1026 } else if (instr->IsMiscDP3SourceOp()) { 1045 } else if (instr->IsMiscDP3SourceOp()) {
1027 DecodeMiscDP3Source(instr); 1046 DecodeMiscDP3Source(instr);
1028 } else if (instr->IsConditionalSelectOp()) { 1047 } else if (instr->IsConditionalSelectOp()) {
1029 DecodeConditionalSelect(instr); 1048 DecodeConditionalSelect(instr);
1030 } else { 1049 } else {
1031 Unknown(instr); 1050 Unknown(instr);
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1386 human_buffer, 1405 human_buffer,
1387 sizeof(human_buffer), 1406 sizeof(human_buffer),
1388 pc); 1407 pc);
1389 pc += instruction_length; 1408 pc += instruction_length;
1390 } 1409 }
1391 } 1410 }
1392 1411
1393 } // namespace dart 1412 } // namespace dart
1394 1413
1395 #endif // defined TARGET_ARCH_ARM 1414 #endif // defined TARGET_ARCH_ARM
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