Adds ldp and stp instructions to ARM64.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 87 matching lines @@
     encoding_ = other.encoding_;
     type_ = other.type_;
     base_ = other.base_;
     return *this;
   }
 
   enum AddressType {
     Offset,
     PreIndex,
     PostIndex,
+    PairOffset,
+    PairPreIndex,
+    PairPostIndex,
     Reg,
     PCOffset,
     Unknown,
   };
 
   // Offset is in bytes. For the unsigned imm12 case, we unscale based on the
   // operand size, and assert that offset is aligned accordingly.
   // For the smaller signed imm9 case, the offset is the number of bytes, but
   // is unscaled.
   Address(Register rn, int32_t offset = 0, AddressType at = Offset,
           OperandSize sz = kDoubleWord) {
     ASSERT((rn != R31) && (rn != ZR));
     ASSERT(CanHoldOffset(offset, at, sz));
     const Register crn = ConcreteRegister(rn);
     const int32_t scale = Log2OperandSizeBytes(sz);
     if ((at == Offset) &&
          Utils::IsUint(12 + scale, offset) &&
         (offset == ((offset >> scale) << scale))) {
       encoding_ =
           B24 |
           ((offset >> scale) << kImm12Shift) |
           (static_cast<int32_t>(crn) << kRnShift);
     } else if ((at == Offset) &&
                Utils::IsInt(9, offset)) {
       encoding_ =
           ((offset & 0x1ff) << kImm9Shift) |
           (static_cast<int32_t>(crn) << kRnShift);
-    } else {
+    } else if ((at == PreIndex) || (at == PostIndex)) {
       ASSERT(Utils::IsInt(9, offset));
-      ASSERT((at == PreIndex) || (at == PostIndex));
       int32_t idx = (at == PostIndex) ? B10 : (B11 | B10);
       encoding_ =
           idx |
           ((offset & 0x1ff) << kImm9Shift) |
           (static_cast<int32_t>(crn) << kRnShift);
+    } else {
+      ASSERT((at == PairOffset) || (at == PairPreIndex) ||
+             (at == PairPostIndex));
+      ASSERT(Utils::IsInt(7 + scale, offset) &&
+             (offset == ((offset >> scale) << scale)));
+      int32_t idx = 0;
+      switch (at) {
+        case PairPostIndex: idx = B23; break;
+        case PairPreIndex: idx = B24 | B23; break;
+        case PairOffset: idx = B24; break;
+        default: UNREACHABLE(); break;
+      }
+      encoding_ =
+        idx |
+        (((offset >> scale) << kImm7Shift) & kImm7Mask) |
+        (static_cast<int32_t>(crn) << kRnShift);
     }
     type_ = at;
     base_ = crn;
   }
 
   // This addressing mode does not exist.
   Address(Register rn, Register offset, AddressType at,
           OperandSize sz = kDoubleWord);
 
   static bool CanHoldOffset(int32_t offset, AddressType at = Offset,
                             OperandSize sz = kDoubleWord) {
     if (at == Offset) {
       // Offset fits in 12 bit unsigned and has right alignment for sz,
       // or fits in 9 bit signed offset with no alignment restriction.
       const int32_t scale = Log2OperandSizeBytes(sz);
       return (Utils::IsUint(12 + scale, offset) &&
               (offset == ((offset >> scale) << scale))) ||
              (Utils::IsInt(9, offset));
     } else if (at == PCOffset) {
       return Utils::IsInt(21, offset) &&
              (offset == ((offset >> 2) << 2));
+    } else if ((at == PreIndex) || (at == PostIndex)) {
+      return Utils::IsInt(9, offset);
     } else {
-      ASSERT((at == PreIndex) || (at == PostIndex));
-      return Utils::IsInt(9, offset);
+      ASSERT((at == PairOffset) || (at == PairPreIndex) ||
+             (at == PairPostIndex));
+      const int32_t scale = Log2OperandSizeBytes(sz);
+      return (Utils::IsInt(7 + scale, offset) &&
+              (offset == ((offset >> scale) << scale)));
     }
   }
 
   // PC-relative load address.
   static Address PC(int32_t pc_off) {
     ASSERT(CanHoldOffset(pc_off, PCOffset));
     Address addr;
     addr.encoding_ = (((pc_off >> 2) << kImm19Shift) & kImm19Mask);
     addr.base_ = kNoRegister;
     addr.type_ = PCOffset;
     return addr;
   }
 
+  static Address Pair(Register rn,
+                      int32_t offset = 0,
+                      AddressType at = PairOffset,
+                      OperandSize sz = kDoubleWord) {
+    return Address(rn, offset, at, sz);
+  }
+
   // This addressing mode does not exist.
   static Address PC(Register r);
 
   enum Scaling {
     Unscaled,
     Scaled,
   };
 
   // Base register rn with offset rm. rm is sign-extended according to ext.
   // If ext is UXTX, rm may be optionally scaled by the
@@ skipping 433 matching lines @@
     EmitMoveWideOp(MOVN, crd, imm, hw_idx, kDoubleWord);
   }
   void movz(Register rd, const Immediate& imm, int hw_idx) {
     ASSERT(rd != CSP);
     const Register crd = ConcreteRegister(rd);
     EmitMoveWideOp(MOVZ, crd, imm, hw_idx, kDoubleWord);
   }
 
   // Loads and Stores.
   void ldr(Register rt, Address a, OperandSize sz = kDoubleWord) {
+    ASSERT((a.type() != Address::PairOffset) &&
+           (a.type() != Address::PairPostIndex) &&
+           (a.type() != Address::PairPreIndex));
     if (a.type() == Address::PCOffset) {
       ASSERT(sz == kDoubleWord);
       EmitLoadRegLiteral(LDRpc, rt, a, sz);
     } else {
       // If we are doing pre-/post-indexing, and the base and result registers
       // are the same, then the result of the load will be clobbered by the
       // writeback, which is unlikely to be useful.
       ASSERT(((a.type() != Address::PreIndex) &&
               (a.type() != Address::PostIndex)) ||
              (rt != a.base()));
       if (IsSignedOperand(sz)) {
         EmitLoadStoreReg(LDRS, rt, a, sz);
       } else {
         EmitLoadStoreReg(LDR, rt, a, sz);
       }
     }
   }
   void str(Register rt, Address a, OperandSize sz = kDoubleWord) {
+    ASSERT((a.type() != Address::PairOffset) &&
+           (a.type() != Address::PairPostIndex) &&
+           (a.type() != Address::PairPreIndex));
     EmitLoadStoreReg(STR, rt, a, sz);
   }
 
+  void ldp(Register rt, Register rt2, Address a, OperandSize sz = kDoubleWord) {
+    ASSERT((a.type() == Address::PairOffset) ||
+           (a.type() == Address::PairPostIndex) ||
+           (a.type() == Address::PairPreIndex));
+    EmitLoadStoreRegPair(LDP, rt, rt2, a, sz);
+  }
+  void stp(Register rt, Register rt2, Address a, OperandSize sz = kDoubleWord) {
+    ASSERT((a.type() == Address::PairOffset) ||
+           (a.type() == Address::PairPostIndex) ||
+           (a.type() == Address::PairPreIndex));
+    EmitLoadStoreRegPair(STP, rt, rt2, a, sz);
+  }
+
   // Conditional select.
   void csel(Register rd, Register rn, Register rm, Condition cond) {
     EmitConditionalSelect(CSEL, rd, rn, rm, cond, kDoubleWord);
   }
   void csinc(Register rd, Register rn, Register rm, Condition cond) {
     EmitConditionalSelect(CSINC, rd, rn, rm, cond, kDoubleWord);
   }
   void cinc(Register rd, Register rn, Condition cond) {
     csinc(rd, rn, rn, InvertCondition(cond));
   }
@@ skipping 930 matching lines @@
     ASSERT((rt != CSP) && (rt != R31));
     const Register crt = ConcreteRegister(rt);
     const int32_t size = (sz == kDoubleWord) ? B30 : 0;
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(crt) << kRtShift) |
         a.encoding();
     Emit(encoding);
   }
 
+  void EmitLoadStoreRegPair(LoadStoreRegPairOp op,
+                            Register rt, Register rt2, Address a,
+                            OperandSize sz) {
+    ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
+    ASSERT((rt != CSP) && (rt != R31));
+    ASSERT((rt2 != CSP) && (rt2 != R31));
+    const Register crt = ConcreteRegister(rt);
+    const Register crt2 = ConcreteRegister(rt2);
+    int32_t opc;
+    switch (sz) {
+      case kDoubleWord: opc = B31; break;
+      case kWord: opc = B30; break;
+      case kUnsignedWord: opc = 0; break;
+      default: UNREACHABLE(); break;
+    }
+    const int32_t encoding =
+      opc | op |
+      (static_cast<int32_t>(crt) << kRtShift) |
+      (static_cast<int32_t>(crt2) << kRt2Shift) |
+      a.encoding();
+    Emit(encoding);
+  }
+
   void EmitPCRelOp(PCRelOp op, Register rd, const Immediate& imm) {
     ASSERT(Utils::IsInt(21, imm.value()));
     ASSERT((rd != R31) && (rd != CSP));
     const Register crd = ConcreteRegister(rd);
     const int32_t loimm = (imm.value() & 0x3) << 29;
     const int32_t hiimm = ((imm.value() >> 2) << kImm19Shift) & kImm19Mask;
     const int32_t encoding =
         op | loimm | hiimm |
         (static_cast<int32_t>(crd) << kRdShift);
     Emit(encoding);
@@ skipping 134 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_