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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include "vm/globals.h" | 5 #include "vm/globals.h" |
| 6 #if defined(TARGET_ARCH_MIPS) | 6 #if defined(TARGET_ARCH_MIPS) |
| 7 | 7 |
| 8 #include "vm/assembler.h" | 8 #include "vm/assembler.h" |
| 9 #include "vm/longjump.h" | 9 #include "vm/longjump.h" |
| 10 #include "vm/runtime_entry.h" | 10 #include "vm/runtime_entry.h" |
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| 623 lw(result, FieldAddress(CTX, Context::isolate_offset())); | 623 lw(result, FieldAddress(CTX, Context::isolate_offset())); |
| 624 const intptr_t table_offset_in_isolate = | 624 const intptr_t table_offset_in_isolate = |
| 625 Isolate::class_table_offset() + ClassTable::table_offset(); | 625 Isolate::class_table_offset() + ClassTable::table_offset(); |
| 626 lw(result, Address(result, table_offset_in_isolate)); | 626 lw(result, Address(result, table_offset_in_isolate)); |
| 627 sll(TMP, TMP, 2); | 627 sll(TMP, TMP, 2); |
| 628 addu(result, result, TMP); | 628 addu(result, result, TMP); |
| 629 lw(result, Address(result)); | 629 lw(result, Address(result)); |
| 630 } | 630 } |
| 631 | 631 |
| 632 | 632 |
| 633 void Assembler::EnterStubFrame(bool uses_pp) { | 633 void Assembler::EnterFrame() { |
| 634 addiu(SP, SP, Immediate(-2 * kWordSize)); |
| 635 sw(RA, Address(SP, 1 * kWordSize)); |
| 636 sw(FP, Address(SP, 0 * kWordSize)); |
| 637 mov(FP, SP); |
| 638 } |
| 639 |
| 640 |
| 641 void Assembler::LeaveFrameAndReturn() { |
| 642 mov(SP, FP); |
| 643 lw(RA, Address(SP, 1 * kWordSize)); |
| 644 lw(FP, Address(SP, 0 * kWordSize)); |
| 645 Ret(); |
| 646 delay_slot()->addiu(SP, SP, Immediate(2 * kWordSize)); |
| 647 } |
| 648 |
| 649 |
| 650 void Assembler::EnterStubFrame(bool load_pp) { |
| 634 SetPrologueOffset(); | 651 SetPrologueOffset(); |
| 635 if (uses_pp) { | 652 addiu(SP, SP, Immediate(-4 * kWordSize)); |
| 636 addiu(SP, SP, Immediate(-4 * kWordSize)); | 653 sw(ZR, Address(SP, 3 * kWordSize)); // PC marker is 0 in stubs. |
| 637 sw(ZR, Address(SP, 3 * kWordSize)); // PC marker is 0 in stubs. | 654 sw(RA, Address(SP, 2 * kWordSize)); |
| 638 sw(RA, Address(SP, 2 * kWordSize)); | 655 sw(FP, Address(SP, 1 * kWordSize)); |
| 639 sw(FP, Address(SP, 1 * kWordSize)); | 656 sw(PP, Address(SP, 0 * kWordSize)); |
| 640 sw(PP, Address(SP, 0 * kWordSize)); | 657 addiu(FP, SP, Immediate(1 * kWordSize)); |
| 641 addiu(FP, SP, Immediate(1 * kWordSize)); | 658 if (load_pp) { |
| 642 // Setup pool pointer for this stub. | 659 // Setup pool pointer for this stub. |
| 643 | 660 LoadPoolPointer(); |
| 644 GetNextPC(TMP); // TMP gets the address of the next instruction. | |
| 645 | |
| 646 const intptr_t object_pool_pc_dist = | |
| 647 Instructions::HeaderSize() - Instructions::object_pool_offset() + | |
| 648 CodeSize(); | |
| 649 | |
| 650 lw(PP, Address(TMP, -object_pool_pc_dist)); | |
| 651 } else { | |
| 652 addiu(SP, SP, Immediate(-3 * kWordSize)); | |
| 653 sw(ZR, Address(SP, 2 * kWordSize)); // PC marker is 0 in stubs. | |
| 654 sw(RA, Address(SP, 1 * kWordSize)); | |
| 655 sw(FP, Address(SP, 0 * kWordSize)); | |
| 656 mov(FP, SP); | |
| 657 } | 661 } |
| 658 } | 662 } |
| 659 | 663 |
| 660 | 664 |
| 661 void Assembler::LeaveStubFrame(bool uses_pp) { | 665 void Assembler::LeaveStubFrame() { |
| 662 if (uses_pp) { | 666 addiu(SP, FP, Immediate(-1 * kWordSize)); |
| 663 addiu(SP, FP, Immediate(-1 * kWordSize)); | 667 lw(RA, Address(SP, 2 * kWordSize)); |
| 664 lw(RA, Address(SP, 2 * kWordSize)); | 668 lw(FP, Address(SP, 1 * kWordSize)); |
| 665 lw(FP, Address(SP, 1 * kWordSize)); | 669 lw(PP, Address(SP, 0 * kWordSize)); |
| 666 lw(PP, Address(SP, 0 * kWordSize)); | 670 addiu(SP, SP, Immediate(4 * kWordSize)); |
| 667 addiu(SP, SP, Immediate(4 * kWordSize)); | |
| 668 } else { | |
| 669 mov(SP, FP); | |
| 670 lw(RA, Address(SP, 1 * kWordSize)); | |
| 671 lw(FP, Address(SP, 0 * kWordSize)); | |
| 672 addiu(SP, SP, Immediate(3 * kWordSize)); | |
| 673 } | |
| 674 } | 671 } |
| 675 | 672 |
| 676 | 673 |
| 677 void Assembler::LeaveStubFrameAndReturn(Register ra, bool uses_pp) { | 674 void Assembler::LeaveStubFrameAndReturn(Register ra) { |
| 678 if (uses_pp) { | 675 addiu(SP, FP, Immediate(-1 * kWordSize)); |
| 679 addiu(SP, FP, Immediate(-1 * kWordSize)); | 676 lw(RA, Address(SP, 2 * kWordSize)); |
| 680 lw(RA, Address(SP, 2 * kWordSize)); | 677 lw(FP, Address(SP, 1 * kWordSize)); |
| 681 lw(FP, Address(SP, 1 * kWordSize)); | 678 lw(PP, Address(SP, 0 * kWordSize)); |
| 682 lw(PP, Address(SP, 0 * kWordSize)); | 679 jr(ra); |
| 683 jr(ra); | 680 delay_slot()->addiu(SP, SP, Immediate(4 * kWordSize)); |
| 684 delay_slot()->addiu(SP, SP, Immediate(4 * kWordSize)); | |
| 685 } else { | |
| 686 mov(SP, FP); | |
| 687 lw(RA, Address(SP, 1 * kWordSize)); | |
| 688 lw(FP, Address(SP, 0 * kWordSize)); | |
| 689 jr(ra); | |
| 690 delay_slot()->addiu(SP, SP, Immediate(3 * kWordSize)); | |
| 691 } | |
| 692 } | 681 } |
| 693 | 682 |
| 694 | 683 |
| 695 void Assembler::TryAllocate(const Class& cls, | 684 void Assembler::TryAllocate(const Class& cls, |
| 696 Label* failure, | 685 Label* failure, |
| 697 Register instance_reg) { | 686 Register instance_reg) { |
| 698 ASSERT(failure != NULL); | 687 ASSERT(failure != NULL); |
| 699 if (FLAG_inline_alloc) { | 688 if (FLAG_inline_alloc) { |
| 700 Heap* heap = Isolate::Current()->heap(); | 689 Heap* heap = Isolate::Current()->heap(); |
| 701 const intptr_t instance_size = cls.instance_size(); | 690 const intptr_t instance_size = cls.instance_size(); |
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| 977 Emit(reinterpret_cast<int32_t>(message)); | 966 Emit(reinterpret_cast<int32_t>(message)); |
| 978 Bind(&msg); | 967 Bind(&msg); |
| 979 break_(Instr::kMsgMessageCode); | 968 break_(Instr::kMsgMessageCode); |
| 980 } | 969 } |
| 981 #endif | 970 #endif |
| 982 } | 971 } |
| 983 | 972 |
| 984 } // namespace dart | 973 } // namespace dart |
| 985 | 974 |
| 986 #endif // defined TARGET_ARCH_MIPS | 975 #endif // defined TARGET_ARCH_MIPS |
| 987 | |
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