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1 // Copyright 2014 The Crashpad Authors. All rights reserved. | 1 // Copyright 2014 The Crashpad Authors. All rights reserved. |
2 // | 2 // |
3 // Licensed under the Apache License, Version 2.0 (the "License"); | 3 // Licensed under the Apache License, Version 2.0 (the "License"); |
4 // you may not use this file except in compliance with the License. | 4 // you may not use this file except in compliance with the License. |
5 // You may obtain a copy of the License at | 5 // You may obtain a copy of the License at |
6 // | 6 // |
7 // http://www.apache.org/licenses/LICENSE-2.0 | 7 // http://www.apache.org/licenses/LICENSE-2.0 |
8 // | 8 // |
9 // Unless required by applicable law or agreed to in writing, software | 9 // Unless required by applicable law or agreed to in writing, software |
10 // distributed under the License is distributed on an "AS IS" BASIS, | 10 // distributed under the License is distributed on an "AS IS" BASIS, |
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220 context->r15 = x86_thread_state64->__r15; | 220 context->r15 = x86_thread_state64->__r15; |
221 context->rip = x86_thread_state64->__rip; | 221 context->rip = x86_thread_state64->__rip; |
222 context->rflags = x86_thread_state64->__rflags; | 222 context->rflags = x86_thread_state64->__rflags; |
223 context->cs = x86_thread_state64->__cs; | 223 context->cs = x86_thread_state64->__cs; |
224 context->fs = x86_thread_state64->__fs; | 224 context->fs = x86_thread_state64->__fs; |
225 context->gs = x86_thread_state64->__gs; | 225 context->gs = x86_thread_state64->__gs; |
226 } | 226 } |
227 | 227 |
228 void InitializeCPUContextX86_64Float( | 228 void InitializeCPUContextX86_64Float( |
229 CPUContextX86_64* context, const x86_float_state64_t* x86_float_state64) { | 229 CPUContextX86_64* context, const x86_float_state64_t* x86_float_state64) { |
230 // This relies on both x86_float_state64_t and context->fxsave64 having | 230 // This relies on both x86_float_state64_t and context->fxsave having |
231 // identical (fxsave64) layout. | 231 // identical (fxsave) layout. |
232 static_assert(offsetof(x86_float_state64_t, __fpu_reserved1) - | 232 static_assert(offsetof(x86_float_state64_t, __fpu_reserved1) - |
233 offsetof(x86_float_state64_t, __fpu_fcw) == | 233 offsetof(x86_float_state64_t, __fpu_fcw) == |
234 sizeof(context->fxsave64), | 234 sizeof(context->fxsave), |
235 "types must be equivalent"); | 235 "types must be equivalent"); |
236 | 236 |
237 memcpy(&context->fxsave64, | 237 memcpy(&context->fxsave, |
238 &x86_float_state64->__fpu_fcw, | 238 &x86_float_state64->__fpu_fcw, |
239 sizeof(context->fxsave64)); | 239 sizeof(context->fxsave)); |
240 } | 240 } |
241 | 241 |
242 void InitializeCPUContextX86_64Debug( | 242 void InitializeCPUContextX86_64Debug( |
243 CPUContextX86_64* context, const x86_debug_state64_t* x86_debug_state64) { | 243 CPUContextX86_64* context, const x86_debug_state64_t* x86_debug_state64) { |
244 context->dr0 = x86_debug_state64->__dr0; | 244 context->dr0 = x86_debug_state64->__dr0; |
245 context->dr1 = x86_debug_state64->__dr1; | 245 context->dr1 = x86_debug_state64->__dr1; |
246 context->dr2 = x86_debug_state64->__dr2; | 246 context->dr2 = x86_debug_state64->__dr2; |
247 context->dr3 = x86_debug_state64->__dr3; | 247 context->dr3 = x86_debug_state64->__dr3; |
248 context->dr4 = x86_debug_state64->__dr4; | 248 context->dr4 = x86_debug_state64->__dr4; |
249 context->dr5 = x86_debug_state64->__dr5; | 249 context->dr5 = x86_debug_state64->__dr5; |
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431 if (set_flavor != x86_DEBUG_STATE64) { | 431 if (set_flavor != x86_DEBUG_STATE64) { |
432 InitializeCPUContextX86_64Debug(context, x86_debug_state64); | 432 InitializeCPUContextX86_64Debug(context, x86_debug_state64); |
433 } | 433 } |
434 } | 434 } |
435 | 435 |
436 } // namespace internal | 436 } // namespace internal |
437 | 437 |
438 #endif | 438 #endif |
439 | 439 |
440 } // namespace crashpad | 440 } // namespace crashpad |
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