Delete old x86 validator.

src/trusted/validator/x86/decoder/ncopcode_opcode_flags.enum

Index: src/trusted/validator/x86/decoder/ncopcode_opcode_flags.enum
diff --git a/src/trusted/validator/x86/decoder/ncopcode_opcode_flags.enum b/src/trusted/validator/x86/decoder/ncopcode_opcode_flags.enum
deleted file mode 100644
index 96530fc075238af8307121df4217170fe08c0514..0000000000000000000000000000000000000000
--- a/src/trusted/validator/x86/decoder/ncopcode_opcode_flags.enum
+++ /dev/null
@@ -1,180 +0,0 @@
-# Define set of possible instruction opcode flags that can apply
-# to an instruction. These flags fully define how to parse an
-# x86 instruction. Used by the decoder defined
-# in native_client/src/trusted/validator/x86/decoder.
-
-# Note: The following sufficies are used:
-#    b - 8 bits.
-#    w - 16 bits.
-#    v - 32 bits.
-#    o - 64 bits.
-
-# Indicates the use of a rex pefix that affects the operand size or
-# instruction semantics. Intel's Notation is REX.W. Only applies if
-# decoder is running in 64-bit mode.
-OpcodeUsesRexW
-
-# Indicates that opcode has REX prefix and REX.R is set.
-OpcodeHasRexR
-
-# Defines instruction that uses opcode value 0-7 in the ModRm reg field
-# as an operand. Intel's notation is /digit. Note: This data will be
-# stored in the first operand, using a ModRmOpcode operand kind.
-OpcodeInModRm
-
-# Defines a special 3DNOW 0F0F format instruction, which is used
-# to parse all 3DNOW OFOF instructions, including the operands,
-# and the trailing opcode in the immediate byte following the instruction.
-Opcode0F0F
-
-# Defines instruction that uses opcode value 0-7 in the ModRm r/m field
-# as an operand (in addition to the ModRm reg field). Note: These
-# instructions also require the ModRm mod field to be 0x3. See
-# section A.2.5 in the Intel manual (see ncdecode_tablegen.c for reference).
-OpcodeInModRmRm
-
-# Defines an OpcodeInModRm, where the value of ModRm must also be less
-# than 0xC0 (see x87 instructions for examples of this).
-# NOTE: When this flag is set, so is OpcodeInModRm.
-# NOTE: Also automatically added when an M_Operand is specified, so that
-# none of the mod=0x3 registers are allowed.
-OpcodeLtC0InModRm
-
-# Defines requirement during instruction matching that the ModRm mod field
-# must be 0x3.
-ModRmModIs0x3
-
-# Defines requirement during instruction matching that the ModRm mod field
-# must not be 0x3.
-ModRmModIsnt0x3
-
-# Defines requirement that the S_Operand value (modrm reg field) can only be
-# 0..5.
-ModRmRegSOperand
-
-# Defines instruction that the ModR/M byte contains a register operand and
-# an r/m operand. Intel's notation is /r.
-OpcodeUsesModRm
-
-# Defines the size of the immediate value that must follow the opcode.
-# Intel's notation is ib, iw, id, and io.
-OpcodeHasImmed
-OpcodeHasImmed_b
-OpcodeHasImmed_w
-OpcodeHasImmed_v
-OpcodeHasImmed_p  # 6 bytes.
-OpcodeHasImmed_o
-OpcodeHasImmed_z  # if effective size 2 bytes, 2 bytes. Otherwise 4 bytes.
-
-# Define the size of the second immediate value that must follow the first
-# immediate opcode (if more than one immediate value).
-OpcodeHasImmed2_b
-OpcodeHasImmed2_w
-OpcodeHasImmed2_v
-
-# Define the size of the immediate value that must follow the opcode, but
-# uses the address size instead of the operand size.
-OpcodeHasImmed_Addr
-
-# Defines a register code, from 0 through 7, added to the hexadecimal byte
-# associated with the instruction, based on the operand size.
-# Intel's notation is +rb. See Intel manual, table 3-1 for details.
-# Note: to compute value 0-7, see first operand, which should be OperandBase.
-OpcodePlusR
-
-# Defines a number used in floating-point instructions when one of the
-# operands is ST(i) from the FPU register stack. The number i (which can
-# range from 0 to 7) is added to the hexidecimal byte given at the left
-# of the plus sign to form a single opcode byte. Intel's notation is +i.
-# Note: to compute value 0-7, see first operand, which sould be OperandBase.
-OpcodePlusI
-
-# Defines that in 64-bit mode, REX prefix should appear if using a 64-bit
-# only register. Only applicable if running in 64-bit mode.
-OpcodeRex
-
-# Indicates the REX prefix does not affect the legacy instruction in 64-bit
-# mode. Intel's notation is N.P.
-OpcodeLegacy
-
-# Defines that the opcode can be prefixed with a lock prefix.
-OpcodeLockable
-
-# Defines that the opcode can be prefixed with a REP prefix.
-OpcodeAllowsRep
-
-# Defines that the opcode can be prefixed with a REPNE prefix.
-OpcodeAllowsRepne
-
-# Defines that the opcode can be prefixed with a DATA16 prefix.
-OpcodeAllowsData16
-
-# Defines that prefix 66 can't be used to define operand size.
-# That is, only 32 or 64 bit values are allowed.
-# Used for special cases where operand size is defined as "d/q".
-# Also used to mark instructions with 66 prefix.
-SizeIgnoresData16
-
-# Defines the expected size of the operand. Can be repeated.
-# The (possibly repeated) flags define the set possible operand
-# sizes that are allowed by the opcode.
-OperandSize_b
-OperandSize_w
-OperandSize_v
-OperandSize_o
-
-# Defines the expected size of addresses. Can be repeated.
-# The (possibly repeated) flags define the set of possible
-# address sizes that are allowed by the opcode.
-AddressSize_w
-AddressSize_v
-AddressSize_o
-
-# The instruction is not allowed by the Native Client Validator.
-NaClIllegal
-
-# Operand size defaults to size 64 in 64-bit mode.
-OperandSizeDefaultIs64
-
-# Operand size must be 64 in 64-bit mode.
-OperandSizeForce64
-
-# The instruction requires that the CPUID sets bit 29 (long mode).
-LongMode
-
-# Ignore multiple 66 prefices when counting the number of prefices allowed
-# in NACL.
-IgnorePrefixDATA16
-
-#
-#--------------------------------------------------------------
-#
-# Note: instructions below this point are used elsewhere within native
-# client, and do not effect the x86 instruction decoder.
-
-
-# Opcode only applies if running in 32-bit mode.
-# Used by the table generator to decide if the instruction
-# should be included in the set of generated tables.
-Opcode32Only
-
-# Opcode only applies if running in 64-bit mode.
-# Used by the table generator to decide if the instruction
-# should be included in the set of generated tables.
-Opcode64Only
-
-# Mark instruction as (unconditional) jump. Used by the x86-64
-# validator to quickly categorize unconditional jumps.
-JumpInstruction
-
-# Mark instruction as conditional jump. Used by the x86-64
-# validator to quickly categorize unconditional jumps.
-ConditionalJump
-
-# Mark instruction as allowing branch hints 2e and 3e.
-BranchHints
-
-# Mark the instruction as partial. This communicates to the print routines
-# that the matched instruction is NOT a valid x86 instruction. Hence, it should
-# use different print rules to better communicate what was partially matched.
-PartialInstruction