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Issue 625923004: Delete old x86 validator. (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client
Patch Set: rebase master Created 6 years, 2 months ago
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1 0000000000000000: 00 c0 add %al, %al
2 00 386 OpcodeUsesModRm OpcodeLockable OperandSize_b
3 Add $Eb, $Gb
4 E_Operand OpUse OpSet
5 G_Operand OpUse
6 NaClExpVector[4] = {
7 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
8 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
9 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
10 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
11 };
12 0000000000000000: 01 c0 add %eax, %eax
13 01 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
14 Add $Ev, $Gv
15 E_Operand OpUse OpSet OperandZeroExtends_v
16 G_Operand OpUse
17 NaClExpVector[4] = {
18 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
19 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
20 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
21 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
22 };
23 0000000000000000: 41 01 c3 add %r11d, %eax
24 01 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
25 Add $Ev, $Gv
26 E_Operand OpUse OpSet OperandZeroExtends_v
27 G_Operand OpUse
28 NaClExpVector[4] = {
29 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
30 { ExprRegister[0] , %r11d, ExprSet | ExprUsed | ExprSize32 },
31 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
32 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
33 };
34 0000000000000000: 44 01 d8 add %eax, %r11d
35 01 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
36 Add $Ev, $Gv
37 E_Operand OpUse OpSet OperandZeroExtends_v
38 G_Operand OpUse
39 NaClExpVector[4] = {
40 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
41 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
42 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
43 { ExprRegister[0] , %r11d, ExprUsed | ExprSize32 },
44 };
45 0000000000000000: 48 01 c3 add %rbx, %rax
46 01 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
47 Add $Ev, $Gv
48 E_Operand OpUse OpSet OperandZeroExtends_v
49 G_Operand OpUse
50 NaClExpVector[4] = {
51 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
52 { ExprRegister[0] , %rbx, ExprSet | ExprUsed | ExprSize64 },
53 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
54 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
55 };
56 0000000000000000: 67 03 18 add %ebx, [%eax]
57 03 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
58 Add $Gv, $Ev
59 G_Operand OpUse OpSet OperandZeroExtends_v
60 E_Operand OpUse
61 NaClExpVector[8] = {
62 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
63 { ExprRegister[0] , %ebx, ExprSet | ExprUsed | ExprSize32 },
64 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
65 { ExprMemOffset[4] , 0, ExprUsed | ExprSize32 },
66 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
67 { ExprRegister[0] , %unknown, 0 },
68 { ExprConstant[0] , 1, ExprSize8 },
69 { ExprConstant[0] , 0, ExprSize8 },
70 };
71 0000000000000000: 02 04 00 add %al, [%rax+%r ax*1]
72 02 386 OpcodeUsesModRm OpcodeLockable OperandSize_b
73 Add $Gb, $Eb
74 G_Operand OpUse OpSet
75 E_Operand OpUse
76 NaClExpVector[8] = {
77 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
78 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
79 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
80 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
81 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
82 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
83 { ExprConstant[0] , 1, ExprSize8 },
84 { ExprConstant[0] , 0, ExprSize8 },
85 };
86 0000000000000000: 67 02 04 00 add %al, [%eax+%e ax*1]
87 02 386 OpcodeUsesModRm OpcodeLockable OperandSize_b
88 Add $Gb, $Eb
89 G_Operand OpUse OpSet
90 E_Operand OpUse
91 NaClExpVector[8] = {
92 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
93 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
94 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
95 { ExprMemOffset[4] , 0, ExprUsed | ExprSize32 },
96 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
97 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
98 { ExprConstant[0] , 1, ExprSize8 },
99 { ExprConstant[0] , 0, ExprSize8 },
100 };
101 0000000000000000: 48 83 ec 08 sub %rsp, 0x8
102 83 / 5 386 OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed_b OpcodeLockable OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
103 Sub $Ev, $Ib
104 E_Operand OpUse OpSet OperandZeroExtends_v
105 I_Operand OpUse
106 NaClExpVector[4] = {
107 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
108 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
109 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
110 { ExprConstant[0] , 0x8, ExprUsed | ExprSize8 | ExprUnsignedHex },
111 };
112 00000000004003d4: e8 83 00 00 00 call 0x40045c
113 e8 386 OpcodeHasImmed_v OperandSize_v OperandSize_o O perandSizeDefaultIs64 JumpInstruction
114 Call {%rip}, {%rsp}, $Jzd
115 RegRIP OpUse OpSet OpImplicit
116 RegRSP OpUse OpSet OpImplicit
117 J_Operand OpUse OperandNear OperandRelative
118 NaClExpVector[6] = {
119 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
120 { ExprRegister[0] , %rip, ExprSet | ExprUsed | ExprSize64 },
121 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
122 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
123 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
124 { ExprConstant[0] , 0x40045c, ExprUsed | ExprSize32 | ExprSignedHex | ExprJump Target },
125 };
126 00000000004003de: e8 7d 05 00 00 call 0x400960
127 e8 386 OpcodeHasImmed_v OperandSize_v OperandSize_o O perandSizeDefaultIs64 JumpInstruction
128 Call {%rip}, {%rsp}, $Jzd
129 RegRIP OpUse OpSet OpImplicit
130 RegRSP OpUse OpSet OpImplicit
131 J_Operand OpUse OperandNear OperandRelative
132 NaClExpVector[6] = {
133 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
134 { ExprRegister[0] , %rip, ExprSet | ExprUsed | ExprSize64 },
135 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
136 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
137 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
138 { ExprConstant[0] , 0x400960, ExprUsed | ExprSize32 | ExprSignedHex | ExprJump Target },
139 };
140 0000000000000000: c3 [P] dontcare(ille gal)
141 c3 386 NaClIllegal OperandSizeDefaultIs64 PartialInst ruction
142 DontCare
143 NaClExpVector[0] = {
144 };
145 0000000000000000: ff 35 ea 0d 20 00 push [%rip+0x200d ea]
146 ff / 6 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o OperandSizeDefaultIs64
147 Push {%rsp}, $Ev
148 RegRSP OpUse OpSet OpImplicit
149 E_Operand OpUse
150 NaClExpVector[8] = {
151 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
152 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
153 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
154 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
155 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
156 { ExprRegister[0] , %unknown, 0 },
157 { ExprConstant[0] , 1, ExprSize8 },
158 { ExprConstant[0] , 0x200dea, ExprSize32 | ExprSignedHex },
159 };
160 0000000000000000: ff 25 ec 0d 20 00 [P] dontcarejump %rip (s), [%rip+0x200dec] (u)
161 ff / 4 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o OperandSizeDefaultIs64 JumpInstruct ion PartialInstruction
162 DontCareJump %rip, $Ev
163 RegRIP OpSet
164 E_Operand OpUse OperandNear
165 NaClExpVector[8] = {
166 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
167 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
168 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
169 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 | ExprJumpTarget },
170 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
171 { ExprRegister[0] , %unknown, 0 },
172 { ExprConstant[0] , 1, ExprSize8 },
173 { ExprConstant[0] , 0x200dec, ExprSize32 | ExprSignedHex },
174 };
175 0000000000000000: 0f 1f 40 00 [P] dontcare
176 [hard coded] 386 PartialInstruction
177 DontCare
178 NaClExpVector[0] = {
179 };
180 0000000000000000: 68 00 00 00 00 push 0x0
181 68 386 OpcodeHasImmed_z OpcodeAllowsData16 OperandSiz eDefaultIs64
182 Push {%rsp}, $Iz
183 RegRSP OpUse OpSet OpImplicit
184 I_Operand OpUse
185 NaClExpVector[4] = {
186 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
187 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
188 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
189 { ExprConstant[0] , 0x0, ExprUsed | ExprSize32 | ExprUnsignedHex },
190 };
191 0000000000400403: e9 e0 ff ff ff [P] dontcarejump %rip (s), 0x4003e8 (u)
192 e9 386 OpcodeHasImmed_v OperandSize_v OperandSize_o O perandSizeDefaultIs64 JumpInstruction PartialInstruction
193 DontCareJump %rip, $Jzd
194 RegRIP OpSet
195 J_Operand OpUse OperandNear OperandRelative
196 NaClExpVector[4] = {
197 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
198 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
199 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
200 { ExprConstant[0] , 0x4003e8, ExprUsed | ExprSize32 | ExprSignedHex | ExprJump Target },
201 };
202 0000000000000000: 49 89 d1 mov %r9, %rdx
203 89 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
204 Mov $Ev, $Gv
205 E_Operand OpSet OperandZeroExtends_v
206 G_Operand OpUse
207 NaClExpVector[4] = {
208 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
209 { ExprRegister[0] , %r9, ExprSet | ExprSize64 },
210 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
211 { ExprRegister[0] , %rdx, ExprUsed | ExprSize64 },
212 };
213 0000000000000000: 5e pop %rsi
214 5e - r6 386 OpcodePlusR OpcodeAllowsData16 OperandSize_w O perandSize_v OperandSize_o OperandSizeDefaultIs64
215 Pop {%rsp}, $r8v
216 RegRSP OpUse OpSet OpImplicit
217 G_OpcodeBase OpSet
218 NaClExpVector[4] = {
219 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
220 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
221 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
222 { ExprRegister[0] , %rsi, ExprSet | ExprSize64 },
223 };
224 0000000000000000: 49 c7 c0 c0 08 40 00 mov %r8, 0x4008c0
225 c7 / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed_z OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
226 Mov $Ev, $Iz
227 E_Operand OpSet OperandZeroExtends_v
228 I_Operand OpUse
229 NaClExpVector[4] = {
230 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
231 { ExprRegister[0] , %r8, ExprSet | ExprSize64 },
232 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
233 { ExprConstant[0] , 0x4008c0, ExprUsed | ExprSize32 | ExprUnsignedHex },
234 };
235 0000000000000000: f4 [P] dontcare
236 f4 386 PartialInstruction
237 DontCare
238 NaClExpVector[0] = {
239 };
240 0000000000000000: 48 8b 05 61 0d 20 00 mov %rax, [%rip+0 x200d61]
241 8b 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
242 Mov $Gv, $Ev
243 G_Operand OpSet OperandZeroExtends_v
244 E_Operand OpUse
245 NaClExpVector[8] = {
246 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
247 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
248 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
249 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
250 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
251 { ExprRegister[0] , %unknown, 0 },
252 { ExprConstant[0] , 1, ExprSize8 },
253 { ExprConstant[0] , 0x200d61, ExprSize32 | ExprSignedHex },
254 };
255 0000000000000000: 48 85 c0 [P] dontcare %rax (u), %rax (u)
256 85 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o PartialInstruction
257 DontCare $Ev, $Gv
258 E_Operand OpUse
259 G_Operand OpUse
260 NaClExpVector[4] = {
261 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
262 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
263 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
264 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
265 };
266 000000000040046a: 74 02 [P] dontcarecondj ump %rip (s), 0x40046e (u)
267 74 386 OpcodeHasImmed OperandSize_b ConditionalJump B ranchHints PartialInstruction
268 DontCareCondJump %rip, $Jb
269 RegRIP OpSet
270 J_Operand OpUse OperandNear OperandRelative
271 NaClExpVector[4] = {
272 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
273 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
274 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
275 { ExprConstant[0] , 0x40046e, ExprUsed | ExprSize8 | ExprSignedHex | ExprJumpT arget },
276 };
277 0000000000000000: ff d0 call %rax
278 ff / 2 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o OperandSizeDefaultIs64 JumpInstruct ion
279 Call {%rip}, {%rsp}, $Ev
280 RegRIP OpUse OpSet OpImplicit
281 RegRSP OpUse OpSet OpImplicit
282 E_Operand OpUse OperandNear
283 NaClExpVector[6] = {
284 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
285 { ExprRegister[0] , %rip, ExprSet | ExprUsed | ExprSize64 },
286 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
287 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
288 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
289 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 | ExprJumpTarget },
290 };
291 000000000040048d: eb 24 [P] dontcarejump %rip (s), 0x4004b3 (u)
292 eb 386 OpcodeHasImmed OperandSize_b JumpInstruction P artialInstruction
293 DontCareJump %rip, $Jb
294 RegRIP OpSet
295 J_Operand OpUse OperandNear OperandRelative
296 NaClExpVector[4] = {
297 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
298 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
299 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
300 { ExprConstant[0] , 0x4004b3, ExprUsed | ExprSize8 | ExprSignedHex | ExprJumpT arget },
301 };
302 0000000000000000: c9 [P] dontcare(ille gal)
303 c9 386 NaClIllegal OperandSizeDefaultIs64 PartialInst ruction
304 DontCare
305 NaClExpVector[0] = {
306 };
307 0000000000000000: 66 66 2e 0f 1f 84 00 00 00 00 00 [P] dontcare
308 [hard coded] 386 PartialInstruction
309 DontCare
310 NaClExpVector[0] = {
311 };
312 0000000000000000: b8 00 00 00 00 mov %eax, 0x0
313 b8 - r0 386 OpcodeHasImmed OpcodePlusR OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
314 Mov $r8v, $Iv
315 G_OpcodeBase OpSet OperandZeroExtends_v
316 I_Operand OpUse
317 NaClExpVector[4] = {
318 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
319 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
320 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
321 { ExprConstant[0] , 0x0, ExprUsed | ExprSize32 | ExprUnsignedHex },
322 };
323 0000000000000000: bf 20 10 60 00 mov %edi, 0x60102 0
324 bf - r7 386 OpcodeHasImmed OpcodePlusR OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
325 Mov $r8v, $Iv
326 G_OpcodeBase OpSet OperandZeroExtends_v
327 I_Operand OpUse
328 NaClExpVector[4] = {
329 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
330 { ExprRegister[0] , %edi, ExprSet | ExprSize32 },
331 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
332 { ExprConstant[0] , 0x601020, ExprUsed | ExprSize32 | ExprUnsignedHex },
333 };
334 0000000000000000: 48 8b 04 c5 a0 13 60 00 mov %rax, [%rax*8 +0x6013a0]
335 8b 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
336 Mov $Gv, $Ev
337 G_Operand OpSet OperandZeroExtends_v
338 E_Operand OpUse
339 NaClExpVector[8] = {
340 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
341 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
342 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
343 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
344 { ExprRegister[0] , %unknown, 0 },
345 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
346 { ExprConstant[0] , 8, ExprSize8 },
347 { ExprConstant[0] , 0x6013a0, ExprSize32 | ExprSignedHex },
348 };
349 0000000000000000: 89 7d fc mov [%rbp-0x4], % edi
350 89 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
351 Mov $Ev, $Gv
352 E_Operand OpSet OperandZeroExtends_v
353 G_Operand OpUse
354 NaClExpVector[8] = {
355 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
356 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
357 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
358 { ExprRegister[0] , %unknown, 0 },
359 { ExprConstant[0] , 1, ExprSize8 },
360 { ExprConstant[0] , -0x4, ExprSize8 | ExprSignedHex },
361 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
362 { ExprRegister[0] , %edi, ExprUsed | ExprSize32 },
363 };
364 0000000000000000: 3b 45 fc [P] dontcare %eax (u), [%rbp-0x4] (u)
365 3b 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o PartialInstruction
366 DontCare $Gv, $Ev
367 G_Operand OpUse
368 E_Operand OpUse
369 NaClExpVector[8] = {
370 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
371 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
372 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
373 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
374 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
375 { ExprRegister[0] , %unknown, 0 },
376 { ExprConstant[0] , 1, ExprSize8 },
377 { ExprConstant[0] , -0x4, ExprSize8 | ExprSignedHex },
378 };
379 0000000000000000: 83 7d f8 08 [P] dontcare [%rb p-0x8] (u), 0x8 (u)
380 83 / 7 386 OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
381 DontCare $Ev, $Ib
382 E_Operand OpUse
383 I_Operand OpUse
384 NaClExpVector[8] = {
385 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
386 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
387 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
388 { ExprRegister[0] , %unknown, 0 },
389 { ExprConstant[0] , 1, ExprSize8 },
390 { ExprConstant[0] , -0x8, ExprSize8 | ExprSignedHex },
391 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
392 { ExprConstant[0] , 0x8, ExprUsed | ExprSize8 | ExprUnsignedHex },
393 };
394 0000000000000000: 8b 45 fc mov %eax, [%rbp-0 x4]
395 8b 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
396 Mov $Gv, $Ev
397 G_Operand OpSet OperandZeroExtends_v
398 E_Operand OpUse
399 NaClExpVector[8] = {
400 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
401 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
402 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
403 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
404 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
405 { ExprRegister[0] , %unknown, 0 },
406 { ExprConstant[0] , 1, ExprSize8 },
407 { ExprConstant[0] , -0x4, ExprSize8 | ExprSignedHex },
408 };
409 0000000000000000: 41 d3 e4 [P] dontcare %r12 d (su), %cl (u)
410 d3 / 4 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
411 DontCare $Ev, %cl
412 E_Operand OpUse OpSet
413 RegCL OpUse
414 NaClExpVector[4] = {
415 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
416 { ExprRegister[0] , %r12d, ExprSet | ExprUsed | ExprSize32 },
417 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
418 { ExprRegister[0] , %cl, ExprUsed | ExprSize8 },
419 };
420 0000000000000000: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 [P] dontcare
421 [hard coded] 386 PartialInstruction
422 DontCare
423 NaClExpVector[0] = {
424 };
425 0000000000000000: 48 c1 fd 03 [P] dontcare %rbp (su), 0x3 (u)
426 c1 / 7 386 OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
427 DontCare $Ev, $Ib
428 E_Operand OpUse OpSet
429 I_Operand OpUse
430 NaClExpVector[4] = {
431 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
432 { ExprRegister[0] , %rbp, ExprSet | ExprUsed | ExprSize64 },
433 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
434 { ExprConstant[0] , 0x3, ExprUsed | ExprSize8 | ExprUnsignedHex },
435 };
436 0000000000000000: 48 8d 2d 0f 07 20 00 lea %rbp, [%rip+0 x20070f]
437 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
438 Lea $Gv, $M
439 G_Operand OpSet OperandZeroExtends_v
440 M_Operand OpAddress
441 NaClExpVector[8] = {
442 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
443 { ExprRegister[0] , %rbp, ExprSet | ExprSize64 },
444 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
445 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
446 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
447 { ExprRegister[0] , %unknown, 0 },
448 { ExprConstant[0] , 1, ExprSize8 },
449 { ExprConstant[0] , 0x20070f, ExprSize32 | ExprSignedHex },
450 };
451 0000000000000000: a0 88 77 66 55 44 33 22 11 mov %al, [0x11223 34455667788]
452 a0 386 OpcodeHasImmed_Addr OperandSize_b
453 Mov %al, $Ob
454 RegAL OpSet
455 O_Operand OpUse
456 NaClExpVector[8] = {
457 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
458 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
459 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
460 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
461 { ExprRegister[0] , %unknown, 0 },
462 { ExprRegister[0] , %unknown, 0 },
463 { ExprConstant[0] , 1, ExprSize8 },
464 { ExprConstant[0] , 0x1122334455667788, ExprSize64 | ExprUnsignedHex },
465 };
466 0000000000000000: 66 a1 88 77 66 55 44 33 22 11 mov %ax, [0x11223 34455667788]
467 a1 386 OpcodeHasImmed_Addr OpcodeAllowsData16 Operand Size_w OperandSize_v OperandSize_o
468 Mov $rAXv, $Ov
469 RegREAX OpSet OperandZeroExtends_v
470 O_Operand OpUse
471 NaClExpVector[8] = {
472 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
473 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
474 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
475 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
476 { ExprRegister[0] , %unknown, 0 },
477 { ExprRegister[0] , %unknown, 0 },
478 { ExprConstant[0] , 1, ExprSize8 },
479 { ExprConstant[0] , 0x1122334455667788, ExprSize64 | ExprUnsignedHex },
480 };
481 0000000000000000: a2 88 77 66 55 44 33 22 11 mov [0x1122334455 667788], %al
482 a2 386 OpcodeHasImmed_Addr OperandSize_b
483 Mov $Ob, %al
484 O_Operand OpSet
485 RegAL OpUse
486 NaClExpVector[8] = {
487 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
488 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
489 { ExprRegister[0] , %unknown, 0 },
490 { ExprRegister[0] , %unknown, 0 },
491 { ExprConstant[0] , 1, ExprSize8 },
492 { ExprConstant[0] , 0x1122334455667788, ExprSize64 | ExprUnsignedHex },
493 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
494 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
495 };
496 0000000000000000: 66 a3 88 77 66 55 44 33 22 11 mov [0x1122334455 667788], %ax
497 a3 386 OpcodeHasImmed_Addr OpcodeAllowsData16 Operand Size_w OperandSize_v OperandSize_o
498 Mov $Ov, $rAXv
499 O_Operand OpSet OperandZeroExtends_v
500 RegREAX OpUse
501 NaClExpVector[8] = {
502 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
503 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
504 { ExprRegister[0] , %unknown, 0 },
505 { ExprRegister[0] , %unknown, 0 },
506 { ExprConstant[0] , 1, ExprSize8 },
507 { ExprConstant[0] , 0x1122334455667788, ExprSize64 | ExprUnsignedHex },
508 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
509 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
510 };
511 0000000000000000: 48 b8 88 77 66 55 44 33 22 11 mov %rax, 0x11223 34455667788
512 b8 - r0 386 OpcodeHasImmed OpcodePlusR OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
513 Mov $r8v, $Iv
514 G_OpcodeBase OpSet OperandZeroExtends_v
515 I_Operand OpUse
516 NaClExpVector[4] = {
517 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
518 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
519 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
520 { ExprConstant[0] , 0x1122334455667788, ExprUsed | ExprSize64 | ExprUnsignedHe x },
521 };
522 0000000000000000: 44 8a 04 00 mov %r8b, [%rax+% rax*1]
523 8a 386 OpcodeUsesModRm OperandSize_b
524 Mov $Gb, $Eb
525 G_Operand OpSet
526 E_Operand OpUse
527 NaClExpVector[8] = {
528 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
529 { ExprRegister[0] , %r8b, ExprSet | ExprSize8 },
530 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
531 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
532 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
533 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
534 { ExprConstant[0] , 1, ExprSize8 },
535 { ExprConstant[0] , 0, ExprSize8 },
536 };
537 0000000000000000: 8a 44 05 00 mov %al, [%rbp+%r ax*1]
538 8a 386 OpcodeUsesModRm OperandSize_b
539 Mov $Gb, $Eb
540 G_Operand OpSet
541 E_Operand OpUse
542 NaClExpVector[8] = {
543 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
544 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
545 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
546 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
547 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
548 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
549 { ExprConstant[0] , 1, ExprSize8 },
550 { ExprConstant[0] , 0x0, ExprSize8 | ExprSignedHex },
551 };
552 0000000000000000: 42 8a 04 20 mov %al, [%rax+%r 12*1]
553 8a 386 OpcodeUsesModRm OperandSize_b
554 Mov $Gb, $Eb
555 G_Operand OpSet
556 E_Operand OpUse
557 NaClExpVector[8] = {
558 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
559 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
560 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
561 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
562 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
563 { ExprRegister[0] , %r12, ExprUsed | ExprSize64 },
564 { ExprConstant[0] , 1, ExprSize8 },
565 { ExprConstant[0] , 0, ExprSize8 },
566 };
567 0000000000000000: 41 8a 44 05 00 mov %al, [%r13+%r ax*1]
568 8a 386 OpcodeUsesModRm OperandSize_b
569 Mov $Gb, $Eb
570 G_Operand OpSet
571 E_Operand OpUse
572 NaClExpVector[8] = {
573 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
574 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
575 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
576 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
577 { ExprRegister[0] , %r13, ExprUsed | ExprSize64 },
578 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
579 { ExprConstant[0] , 1, ExprSize8 },
580 { ExprConstant[0] , 0x0, ExprSize8 | ExprSignedHex },
581 };
582 0000000000000000: 0f 38 08 2c 25 00 00 00 00 [P] dontcare [0x0 ] (u)
583 0f 38 08 SSSE3 OpcodeUsesModRm PartialInstruction
584 DontCare $Qq
585 Mmx_E_Operand OpUse
586 NaClExpVector[6] = {
587 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
588 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
589 { ExprRegister[0] , %unknown, 0 },
590 { ExprRegister[0] , %unknown, 0 },
591 { ExprConstant[0] , 1, ExprSize8 },
592 { ExprConstant[0] , 0x0, ExprSize32 | ExprSignedHex },
593 };
594 0000000000000000: 66 0f 38 08 2c 25 00 00 00 00 [P] dontcare [0x0 ] (u)
595 66 0f 38 08 SSSE3 OpcodeUsesModRm OpcodeAllowsData16 SizeIgnor esData16 PartialInstruction
596 DontCare $Wdq
597 Xmm_E_Operand OpUse
598 NaClExpVector[6] = {
599 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
600 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
601 { ExprRegister[0] , %unknown, 0 },
602 { ExprRegister[0] , %unknown, 0 },
603 { ExprConstant[0] , 1, ExprSize8 },
604 { ExprConstant[0] , 0x0, ExprSize32 | ExprSignedHex },
605 };
606 0000000000000000: 66 44 0f 38 08 2c 00 [P] dontcare [%ra x+%rax*1] (u)
607 66 0f 38 08 SSSE3 OpcodeUsesModRm OpcodeAllowsData16 SizeIgnor esData16 PartialInstruction
608 DontCare $Wdq
609 Xmm_E_Operand OpUse
610 NaClExpVector[6] = {
611 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
612 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
613 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
614 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
615 { ExprConstant[0] , 1, ExprSize8 },
616 { ExprConstant[0] , 0, ExprSize8 },
617 };
618 0000000000000000: dd 24 00 [P] dontcare [%ra x+%rax*1] (u)
619 dd / 4 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruction
620 DontCare $Mf
621 M_Operand OpUse
622 NaClExpVector[6] = {
623 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
624 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
625 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
626 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
627 { ExprConstant[0] , 1, ExprSize8 },
628 { ExprConstant[0] , 0, ExprSize8 },
629 };
630 0000000000000000: 67 dd 24 00 [P] dontcare [%ea x+%eax*1] (u)
631 dd / 4 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruction
632 DontCare $Mf
633 M_Operand OpUse
634 NaClExpVector[6] = {
635 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
636 { ExprMemOffset[4] , 0, ExprUsed | ExprSize32 },
637 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
638 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
639 { ExprConstant[0] , 1, ExprSize8 },
640 { ExprConstant[0] , 0, ExprSize8 },
641 };
642 0000000000000000: dc c1 [P] dontcare
643 dc c1 X87 PartialInstruction
644 DontCare
645 NaClExpVector[0] = {
646 };
647 0000000000000000: d8 74 24 10 [P] dontcare [%rs p+0x10] (u)
648 d8 / 6 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruction
649 DontCare $Md
650 Mv_Operand OpUse
651 NaClExpVector[6] = {
652 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
653 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
654 { ExprRegister[0] , %rsp, ExprUsed | ExprSize64 },
655 { ExprRegister[0] , %unknown, 0 },
656 { ExprConstant[0] , 1, ExprSize8 },
657 { ExprConstant[0] , 0x10, ExprSize8 | ExprSignedHex },
658 };
659 0000000000000000: 67 d8 74 24 10 [P] dontcare [%es p+0x10] (u)
660 d8 / 6 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruction
661 DontCare $Md
662 Mv_Operand OpUse
663 NaClExpVector[6] = {
664 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
665 { ExprMemOffset[4] , 0, ExprUsed | ExprSize32 },
666 { ExprRegister[0] , %esp, ExprUsed | ExprSize32 },
667 { ExprRegister[0] , %unknown, 0 },
668 { ExprConstant[0] , 1, ExprSize8 },
669 { ExprConstant[0] , 0x10, ExprSize8 | ExprSignedHex },
670 };
671 0000000000000000: dc 44 00 04 [P] dontcare [%ra x+%rax*1+0x4] (u)
672 dc / 0 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruction
673 DontCare $Mq
674 Mo_Operand OpUse
675 NaClExpVector[6] = {
676 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
677 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
678 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
679 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
680 { ExprConstant[0] , 1, ExprSize8 },
681 { ExprConstant[0] , 0x4, ExprSize8 | ExprSignedHex },
682 };
683 0000000000000000: da 04 25 04 00 00 00 [P] dontcare [0x4 ] (u)
684 da / 0 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruction
685 DontCare $Md
686 Mv_Operand OpUse
687 NaClExpVector[6] = {
688 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
689 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
690 { ExprRegister[0] , %unknown, 0 },
691 { ExprRegister[0] , %unknown, 0 },
692 { ExprConstant[0] , 1, ExprSize8 },
693 { ExprConstant[0] , 0x4, ExprSize32 | ExprSignedHex },
694 };
695 0000000000000000: da 70 04 [P] dontcare [%ra x+0x4] (u)
696 da / 6 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruction
697 DontCare $Md
698 Mv_Operand OpUse
699 NaClExpVector[6] = {
700 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
701 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
702 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
703 { ExprRegister[0] , %unknown, 0 },
704 { ExprConstant[0] , 1, ExprSize8 },
705 { ExprConstant[0] , 0x4, ExprSize8 | ExprSignedHex },
706 };
707 0000000000000000: de 50 04 [P] dontcare [%ra x+0x4] (u)
708 de / 2 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruction
709 DontCare $Mw
710 Mw_Operand OpUse
711 NaClExpVector[6] = {
712 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
713 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
714 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
715 { ExprRegister[0] , %unknown, 0 },
716 { ExprConstant[0] , 1, ExprSize8 },
717 { ExprConstant[0] , 0x4, ExprSize8 | ExprSignedHex },
718 };
719 0000000000000000: dc e5 [P] dontcare
720 dc e5 X87 PartialInstruction
721 DontCare
722 NaClExpVector[0] = {
723 };
724 0000000000000000: dc f3 [P] dontcare
725 dc f3 X87 PartialInstruction
726 DontCare
727 NaClExpVector[0] = {
728 };
729 0000000000000000: dc ea [P] dontcare
730 dc ea X87 PartialInstruction
731 DontCare
732 NaClExpVector[0] = {
733 };
734 0000000000000000: dc ce [P] dontcare
735 dc ce X87 PartialInstruction
736 DontCare
737 NaClExpVector[0] = {
738 };
739 0000000000000000: 48 63 c6 [P] dontcare %rax (sz), %esi (u)
740 63 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o LongMode PartialInstruction
741 DontCare $Gv, $Ed
742 G_Operand OpSet OperandZeroExtends_v
743 Ev_Operand OpUse
744 NaClExpVector[4] = {
745 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
746 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
747 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
748 { ExprRegister[0] , %esi, ExprUsed | ExprSize32 },
749 };
750 0000000000000000: 63 c6 [P] dontcare %eax (sz), %esi (u)
751 63 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o LongMode PartialInstruction
752 DontCare $Gv, $Ed
753 G_Operand OpSet OperandZeroExtends_v
754 Ev_Operand OpUse
755 NaClExpVector[4] = {
756 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
757 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
758 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
759 { ExprRegister[0] , %esi, ExprUsed | ExprSize32 },
760 };
761 0000000000000000: 6c [P] dontcare(ille gal)
762 6c 386 OpcodeAllowsRep OperandSize_b NaClIllegal Part ialInstruction
763 DontCare
764 NaClExpVector[0] = {
765 };
766 0000000000000000: 6d [P] dontcare(ille gal)
767 6d 386 OpcodeAllowsRep OperandSize_v OperandSize_o Na ClIllegal PartialInstruction
768 DontCare
769 NaClExpVector[0] = {
770 };
771 0000000000000000: 66 6d [P] dontcare(ille gal)
772 6d 386 OpcodeAllowsRep OpcodeAllowsData16 OperandSize _w NaClIllegal PartialInstruction
773 DontCare
774 NaClExpVector[0] = {
775 };
776 0000000000000000: 6e [P] dontcare(ille gal)
777 6e 386 OpcodeAllowsRep OperandSize_b NaClIllegal Part ialInstruction
778 DontCare
779 NaClExpVector[0] = {
780 };
781 0000000000000000: 6f [P] dontcare(ille gal)
782 6f 386 OpcodeAllowsRep OperandSize_v OperandSize_o Na ClIllegal PartialInstruction
783 DontCare
784 NaClExpVector[0] = {
785 };
786 0000000000000000: 66 6f [P] dontcare(ille gal)
787 6f 386 OpcodeAllowsRep OpcodeAllowsData16 OperandSize _w NaClIllegal PartialInstruction
788 DontCare
789 NaClExpVector[0] = {
790 };
791 0000000000000000: 66 98 [P] dontcare %ax (s), %al (u)
792 98 386 OpcodeAllowsData16 OperandSize_w PartialInstru ction
793 DontCare %ax, %al
794 RegAX OpSet
795 RegAL OpUse
796 NaClExpVector[4] = {
797 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
798 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
799 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
800 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
801 };
802 0000000000000000: 98 [P] dontcare %eax (s), %ax (u)
803 98 386 OperandSize_v PartialInstruction
804 DontCare %eax, %ax
805 RegEAX OpSet OperandSignExtends_v
806 RegAX OpUse
807 NaClExpVector[4] = {
808 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
809 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
810 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
811 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
812 };
813 0000000000000000: 48 98 [P] dontcare %rax (s), %eax (u)
814 98 386 OperandSize_o LongMode PartialInstruction
815 DontCare %rax, %eax
816 RegRAX OpSet
817 RegEAX OpUse
818 NaClExpVector[4] = {
819 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
820 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
821 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
822 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
823 };
824 0000000000000000: 66 99 [P] dontcare %dx (s), %ax (u)
825 99 386 OpcodeAllowsData16 OperandSize_w PartialInstru ction
826 DontCare %dx, %ax
827 RegDX OpSet
828 RegAX OpUse
829 NaClExpVector[4] = {
830 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
831 { ExprRegister[0] , %dx, ExprSet | ExprSize16 },
832 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
833 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
834 };
835 0000000000000000: 99 [P] dontcare %edx (s), %eax (u)
836 99 386 OperandSize_v PartialInstruction
837 DontCare %edx, %eax
838 RegEDX OpSet
839 RegEAX OpUse
840 NaClExpVector[4] = {
841 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
842 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
843 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
844 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
845 };
846 0000000000000000: 48 99 [P] dontcare %rdx (s), %rax (u)
847 99 386 OperandSize_o LongMode PartialInstruction
848 DontCare %rdx, %rax
849 RegRDX OpSet
850 RegRAX OpUse
851 NaClExpVector[4] = {
852 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
853 { ExprRegister[0] , %rdx, ExprSet | ExprSize64 },
854 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
855 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
856 };
857 0000000000000000: 86 c2 [P] dontcare %dl (su), %al (su)
858 86 386 OpcodeUsesModRm OpcodeLockable OperandSize_b P artialInstruction
859 DontCare $Eb, $Gb
860 E_Operand OpUse OpSet
861 G_Operand OpUse OpSet
862 NaClExpVector[4] = {
863 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
864 { ExprRegister[0] , %dl, ExprSet | ExprUsed | ExprSize8 },
865 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
866 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
867 };
868 0000000000000000: 86 40 20 [P] dontcare [%ra x+0x20] (su), %al (su)
869 86 386 OpcodeUsesModRm OpcodeLockable OperandSize_b P artialInstruction
870 DontCare $Eb, $Gb
871 E_Operand OpUse OpSet
872 G_Operand OpUse OpSet
873 NaClExpVector[8] = {
874 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
875 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
876 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
877 { ExprRegister[0] , %unknown, 0 },
878 { ExprConstant[0] , 1, ExprSize8 },
879 { ExprConstant[0] , 0x20, ExprSize8 | ExprSignedHex },
880 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
881 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
882 };
883 0000000000000000: 87 40 20 [P] dontcare [%ra x+0x20] (suz), %eax (suz)
884 87 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
885 DontCare $Ev, $Gv
886 E_Operand OpUse OpSet OperandZeroExtends_v
887 G_Operand OpUse OpSet OperandZeroExtends_v
888 NaClExpVector[8] = {
889 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
890 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
891 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
892 { ExprRegister[0] , %unknown, 0 },
893 { ExprConstant[0] , 1, ExprSize8 },
894 { ExprConstant[0] , 0x20, ExprSize8 | ExprSignedHex },
895 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
896 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
897 };
898 0000000000000000: a6 [P] dontcare [%rd i] (u), [%rsi] (u)
899 a6 386 OpcodeAllowsRep OpcodeAllowsRepne OperandSize_ b PartialInstruction
900 DontCare $Yb, $Xb
901 RegES_EDI OpUse
902 RegDS_ESI OpUse
903 NaClExpVector[8] = {
904 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
905 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
906 { ExprRegister[0] , %es, ExprSize16 },
907 { ExprRegister[0] , %rdi, ExprSize64 },
908 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
909 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
910 { ExprRegister[0] , %ds, ExprSize16 },
911 { ExprRegister[0] , %rsi, ExprSize64 },
912 };
913 0000000000000000: 66 a7 [P] dontcare [%rd i] (u), [%rsi] (u)
914 a7 386 OpcodeAllowsRep OpcodeAllowsRepne OpcodeAllows Data16 OperandSize_w PartialInstruction
915 DontCare $Yvw, $Xvw
916 RegES_EDI OpUse
917 RegDS_ESI OpUse
918 NaClExpVector[8] = {
919 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
920 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
921 { ExprRegister[0] , %es, ExprSize16 },
922 { ExprRegister[0] , %rdi, ExprSize64 },
923 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
924 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
925 { ExprRegister[0] , %ds, ExprSize16 },
926 { ExprRegister[0] , %rsi, ExprSize64 },
927 };
928 0000000000000000: a7 [P] dontcare [%rd i] (u), [%rsi] (u)
929 a7 386 OpcodeAllowsRep OpcodeAllowsRepne OperandSize_ v PartialInstruction
930 DontCare $Yvd, $Xvd
931 RegES_EDI OpUse
932 RegDS_ESI OpUse
933 NaClExpVector[8] = {
934 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
935 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
936 { ExprRegister[0] , %es, ExprSize16 },
937 { ExprRegister[0] , %rdi, ExprSize64 },
938 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
939 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
940 { ExprRegister[0] , %ds, ExprSize16 },
941 { ExprRegister[0] , %rsi, ExprSize64 },
942 };
943 0000000000000000: 48 a7 [P] dontcare [%rd i] (u), [%rsi] (u)
944 a7 386 OpcodeAllowsRep OpcodeAllowsRepne OperandSize_ o LongMode PartialInstruction
945 DontCare $Yvq, $Xvq
946 RegES_EDI OpUse
947 RegDS_ESI OpUse
948 NaClExpVector[8] = {
949 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
950 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
951 { ExprRegister[0] , %es, ExprSize16 },
952 { ExprRegister[0] , %rdi, ExprSize64 },
953 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
954 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
955 { ExprRegister[0] , %ds, ExprSize16 },
956 { ExprRegister[0] , %rsi, ExprSize64 },
957 };
958 0000000000000000: aa [P] dontcare [%rd i] (s), %al (u)
959 aa 386 OpcodeAllowsRep OperandSize_b PartialInstructi on
960 DontCare $Yb, %al
961 RegES_EDI OpSet
962 RegAL OpUse
963 NaClExpVector[6] = {
964 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
965 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
966 { ExprRegister[0] , %es, ExprSize16 },
967 { ExprRegister[0] , %rdi, ExprSize64 },
968 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
969 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
970 };
971 0000000000000000: ab [P] dontcare [%rd i] (s), %eax (u)
972 ab 386 OpcodeAllowsRep OperandSize_v PartialInstructi on
973 DontCare $Yvd, $rAXvd
974 RegES_EDI OpSet
975 RegEAX OpUse
976 NaClExpVector[6] = {
977 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
978 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
979 { ExprRegister[0] , %es, ExprSize16 },
980 { ExprRegister[0] , %rdi, ExprSize64 },
981 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
982 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
983 };
984 0000000000000000: 66 ab [P] dontcare [%rd i] (s), %ax (u)
985 ab 386 OpcodeAllowsRep OpcodeAllowsData16 OperandSize _w PartialInstruction
986 DontCare $Yvw, $rAXvw
987 RegES_EDI OpSet
988 RegAX OpUse
989 NaClExpVector[6] = {
990 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
991 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
992 { ExprRegister[0] , %es, ExprSize16 },
993 { ExprRegister[0] , %rdi, ExprSize64 },
994 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
995 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
996 };
997 0000000000000000: 48 ab [P] dontcare [%rd i] (s), %rax (u)
998 ab 386 OpcodeAllowsRep OperandSize_o LongMode Partial Instruction
999 DontCare $Yvq, $rAXvq
1000 RegES_EDI OpSet
1001 RegRAX OpUse
1002 NaClExpVector[6] = {
1003 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1004 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
1005 { ExprRegister[0] , %es, ExprSize16 },
1006 { ExprRegister[0] , %rdi, ExprSize64 },
1007 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1008 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
1009 };
1010 0000000000000000: a4 [P] dontcare [%rd i] (s), [%rsi] (u)
1011 a4 386 OpcodeAllowsRep OperandSize_b PartialInstructi on
1012 DontCare $Yb, $Xb
1013 RegES_EDI OpSet
1014 RegDS_ESI OpUse
1015 NaClExpVector[8] = {
1016 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1017 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
1018 { ExprRegister[0] , %es, ExprSize16 },
1019 { ExprRegister[0] , %rdi, ExprSize64 },
1020 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1021 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1022 { ExprRegister[0] , %ds, ExprSize16 },
1023 { ExprRegister[0] , %rsi, ExprSize64 },
1024 };
1025 0000000000000000: 66 a5 [P] dontcare [%rd i] (s), [%rsi] (u)
1026 a5 386 OpcodeAllowsRep OpcodeAllowsData16 OperandSize _w PartialInstruction
1027 DontCare $Yvw, $Xvw
1028 RegES_EDI OpSet
1029 RegDS_ESI OpUse
1030 NaClExpVector[8] = {
1031 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1032 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
1033 { ExprRegister[0] , %es, ExprSize16 },
1034 { ExprRegister[0] , %rdi, ExprSize64 },
1035 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1036 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1037 { ExprRegister[0] , %ds, ExprSize16 },
1038 { ExprRegister[0] , %rsi, ExprSize64 },
1039 };
1040 0000000000000000: a5 [P] dontcare [%rd i] (s), [%rsi] (u)
1041 a5 386 OpcodeAllowsRep OperandSize_v PartialInstructi on
1042 DontCare $Yvd, $Xvd
1043 RegES_EDI OpSet
1044 RegDS_ESI OpUse
1045 NaClExpVector[8] = {
1046 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1047 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
1048 { ExprRegister[0] , %es, ExprSize16 },
1049 { ExprRegister[0] , %rdi, ExprSize64 },
1050 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1051 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1052 { ExprRegister[0] , %ds, ExprSize16 },
1053 { ExprRegister[0] , %rsi, ExprSize64 },
1054 };
1055 0000000000000000: 48 a5 [P] dontcare [%rd i] (s), [%rsi] (u)
1056 a5 386 OpcodeAllowsRep OperandSize_o LongMode Partial Instruction
1057 DontCare $Yvq, $Xvq
1058 RegES_EDI OpSet
1059 RegDS_ESI OpUse
1060 NaClExpVector[8] = {
1061 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1062 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
1063 { ExprRegister[0] , %es, ExprSize16 },
1064 { ExprRegister[0] , %rdi, ExprSize64 },
1065 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1066 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1067 { ExprRegister[0] , %ds, ExprSize16 },
1068 { ExprRegister[0] , %rsi, ExprSize64 },
1069 };
1070 0000000000000000: 9c [P] dontcare(ille gal)
1071 9c 386 OperandSize_o NaClIllegal OperandSizeDefaultIs 64 LongMode PartialInstruction
1072 DontCare
1073 NaClExpVector[0] = {
1074 };
1075 0000000000000000: 9d [P] dontcare(ille gal)
1076 9d 386 OperandSize_o NaClIllegal OperandSizeDefaultIs 64 LongMode PartialInstruction
1077 DontCare
1078 NaClExpVector[0] = {
1079 };
1080 0000000000000000: ac [P] dontcare %al (s), [%rsi] (u)
1081 ac 386 OpcodeAllowsRep OperandSize_b PartialInstructi on
1082 DontCare %al, $Xb
1083 RegAL OpSet
1084 RegDS_ESI OpUse
1085 NaClExpVector[6] = {
1086 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1087 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
1088 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1089 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1090 { ExprRegister[0] , %ds, ExprSize16 },
1091 { ExprRegister[0] , %rsi, ExprSize64 },
1092 };
1093 0000000000000000: ad [P] dontcare %eax (s), [%rsi] (u)
1094 ad 386 OpcodeAllowsRep OperandSize_v PartialInstructi on
1095 DontCare $rAXvd, $Xvd
1096 RegEAX OpSet
1097 RegDS_ESI OpUse
1098 NaClExpVector[6] = {
1099 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1100 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
1101 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1102 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1103 { ExprRegister[0] , %ds, ExprSize16 },
1104 { ExprRegister[0] , %rsi, ExprSize64 },
1105 };
1106 0000000000000000: 66 ad [P] dontcare %ax (s), [%rsi] (u)
1107 ad 386 OpcodeAllowsRep OpcodeAllowsData16 OperandSize _w PartialInstruction
1108 DontCare $rAXvw, $Xvw
1109 RegAX OpSet
1110 RegDS_ESI OpUse
1111 NaClExpVector[6] = {
1112 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1113 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
1114 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1115 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1116 { ExprRegister[0] , %ds, ExprSize16 },
1117 { ExprRegister[0] , %rsi, ExprSize64 },
1118 };
1119 0000000000000000: 48 ad [P] dontcare %rax (s), [%rsi] (u)
1120 ad 386 OpcodeAllowsRep OperandSize_o LongMode Partial Instruction
1121 DontCare $rAXvq, $Xvq
1122 RegRAX OpSet
1123 RegDS_ESI OpUse
1124 NaClExpVector[6] = {
1125 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1126 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
1127 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1128 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1129 { ExprRegister[0] , %ds, ExprSize16 },
1130 { ExprRegister[0] , %rsi, ExprSize64 },
1131 };
1132 0000000000000000: ae [P] dontcare %al (u), [%rdi] (u)
1133 ae 386 OpcodeAllowsRep OpcodeAllowsRepne OperandSize_ b PartialInstruction
1134 DontCare %al, $Yb
1135 RegAL OpUse
1136 RegES_EDI OpUse
1137 NaClExpVector[6] = {
1138 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1139 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
1140 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1141 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
1142 { ExprRegister[0] , %es, ExprSize16 },
1143 { ExprRegister[0] , %rdi, ExprSize64 },
1144 };
1145 0000000000000000: af [P] dontcare %eax (u), [%rdi] (u)
1146 af 386 OpcodeAllowsRep OpcodeAllowsRepne OperandSize_ v PartialInstruction
1147 DontCare $rAXvd, $Yvd
1148 RegEAX OpUse
1149 RegES_EDI OpUse
1150 NaClExpVector[6] = {
1151 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1152 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
1153 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1154 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
1155 { ExprRegister[0] , %es, ExprSize16 },
1156 { ExprRegister[0] , %rdi, ExprSize64 },
1157 };
1158 0000000000000000: 66 af [P] dontcare %ax (u), [%rdi] (u)
1159 af 386 OpcodeAllowsRep OpcodeAllowsRepne OpcodeAllows Data16 OperandSize_w PartialInstruction
1160 DontCare $rAXvw, $Yvw
1161 RegAX OpUse
1162 RegES_EDI OpUse
1163 NaClExpVector[6] = {
1164 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1165 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
1166 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1167 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
1168 { ExprRegister[0] , %es, ExprSize16 },
1169 { ExprRegister[0] , %rdi, ExprSize64 },
1170 };
1171 0000000000000000: 48 af [P] dontcare %rax (u), [%rdi] (u)
1172 af 386 OpcodeAllowsRep OpcodeAllowsRepne OperandSize_ o LongMode PartialInstruction
1173 DontCare $rAXvq, $Yvq
1174 RegRAX OpUse
1175 RegES_EDI OpUse
1176 NaClExpVector[6] = {
1177 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1178 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
1179 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1180 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
1181 { ExprRegister[0] , %es, ExprSize16 },
1182 { ExprRegister[0] , %rdi, ExprSize64 },
1183 };
1184 0000000000000000: c8 2c 01 00 [P] dontcare(ille gal)
1185 c8 386 OpcodeHasImmed_w OpcodeHasImmed2_b NaClIllegal OperandSizeDefaultIs64 PartialInstruction
1186 DontCare
1187 NaClExpVector[0] = {
1188 };
1189 0000000000000000: 80 e4 df and %ah, 0xdf
1190 80 / 4 386 OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed O pcodeLockable OperandSize_b
1191 And $Eb, $Ib
1192 E_Operand OpUse OpSet
1193 I_Operand OpUse
1194 NaClExpVector[4] = {
1195 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1196 { ExprRegister[0] , %ah, ExprSet | ExprUsed | ExprSize8 },
1197 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1198 { ExprConstant[0] , 0xdf, ExprUsed | ExprSize8 | ExprUnsignedHex },
1199 };
1200 0000000000000000: 22 24 25 df 00 00 00 and %ah, [0xdf]
1201 22 386 OpcodeUsesModRm OpcodeLockable OperandSize_b
1202 And $Gb, $Eb
1203 G_Operand OpUse OpSet
1204 E_Operand OpUse
1205 NaClExpVector[8] = {
1206 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1207 { ExprRegister[0] , %ah, ExprSet | ExprUsed | ExprSize8 },
1208 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1209 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1210 { ExprRegister[0] , %unknown, 0 },
1211 { ExprRegister[0] , %unknown, 0 },
1212 { ExprConstant[0] , 1, ExprSize8 },
1213 { ExprConstant[0] , 0xdf, ExprSize32 | ExprSignedHex },
1214 };
1215 0000000000000000: 40 22 24 25 df 00 00 00 and %spl, [0xdf]
1216 22 386 OpcodeUsesModRm OpcodeLockable OperandSize_b
1217 And $Gb, $Eb
1218 G_Operand OpUse OpSet
1219 E_Operand OpUse
1220 NaClExpVector[8] = {
1221 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1222 { ExprRegister[0] , %spl, ExprSet | ExprUsed | ExprSize8 },
1223 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1224 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1225 { ExprRegister[0] , %unknown, 0 },
1226 { ExprRegister[0] , %unknown, 0 },
1227 { ExprConstant[0] , 1, ExprSize8 },
1228 { ExprConstant[0] , 0xdf, ExprSize32 | ExprSignedHex },
1229 };
1230 0000000000000000: 8d 04 85 ff ff ff ff lea %eax, [%rax*4 -0x1]
1231 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
1232 Lea $Gv, $M
1233 G_Operand OpSet OperandZeroExtends_v
1234 M_Operand OpAddress
1235 NaClExpVector[8] = {
1236 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1237 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
1238 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1239 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
1240 { ExprRegister[0] , %unknown, 0 },
1241 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
1242 { ExprConstant[0] , 4, ExprSize8 },
1243 { ExprConstant[0] , -0x1, ExprSize32 | ExprSignedHex },
1244 };
1245 0000000000000000: 64 48 33 14 25 28 00 00 00 [P] dontcare %rdx (suz), %fs:[0x28] (u)
1246 33 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1247 DontCare $Gv, $Ev
1248 G_Operand OpUse OpSet OperandZeroExtends_v
1249 E_Operand OpUse
1250 NaClExpVector[10] = {
1251 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1252 { ExprRegister[0] , %rdx, ExprSet | ExprUsed | ExprSize64 },
1253 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1254 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 },
1255 { ExprRegister[0] , %fs, ExprUsed | ExprSize16 },
1256 { ExprMemOffset[4] , 0, ExprSize64 },
1257 { ExprRegister[0] , %unknown, 0 },
1258 { ExprRegister[0] , %unknown, 0 },
1259 { ExprConstant[0] , 1, ExprSize8 },
1260 { ExprConstant[0] , 0x28, ExprSize32 | ExprSignedHex },
1261 };
1262 0000000000000000: 48 b8 cd cc cc cc cc cc cc cc mov %rax, 0xccccc ccccccccccd
1263 b8 - r0 386 OpcodeHasImmed OpcodePlusR OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
1264 Mov $r8v, $Iv
1265 G_OpcodeBase OpSet OperandZeroExtends_v
1266 I_Operand OpUse
1267 NaClExpVector[4] = {
1268 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1269 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
1270 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1271 { ExprConstant[0] , 0xcccccccccccccccd, ExprUsed | ExprSize64 | ExprUnsignedHe x },
1272 };
1273 0000000000000000: 66 6b c0 16 [P] dontcare %ax (sz), %ax (u), 0x16 (u)
1274 6b 386 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsD ata16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1275 DontCare $Gv, $Ev, $Ib
1276 G_Operand OpSet OperandZeroExtends_v
1277 E_Operand OpUse
1278 I_Operand OpUse
1279 NaClExpVector[6] = {
1280 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1281 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
1282 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1283 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
1284 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1285 { ExprConstant[0] , 0x16, ExprUsed | ExprSize8 | ExprUnsignedHex },
1286 };
1287 0000000000000000: 66 6b d8 16 [P] dontcare %bx (sz), %ax (u), 0x16 (u)
1288 6b 386 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsD ata16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1289 DontCare $Gv, $Ev, $Ib
1290 G_Operand OpSet OperandZeroExtends_v
1291 E_Operand OpUse
1292 I_Operand OpUse
1293 NaClExpVector[6] = {
1294 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1295 { ExprRegister[0] , %bx, ExprSet | ExprSize16 },
1296 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1297 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
1298 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1299 { ExprConstant[0] , 0x16, ExprUsed | ExprSize8 | ExprUnsignedHex },
1300 };
1301 0000000000000000: 66 f7 e8 [P] dontcare %dx (s), %ax (su), %ax (u)
1302 f7 / 5 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1303 DontCare %redx, %reax, $Ev
1304 RegREDX OpSet
1305 RegREAX OpUse OpSet
1306 E_Operand OpUse
1307 NaClExpVector[6] = {
1308 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1309 { ExprRegister[0] , %dx, ExprSet | ExprSize16 },
1310 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1311 { ExprRegister[0] , %ax, ExprSet | ExprUsed | ExprSize16 },
1312 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1313 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
1314 };
1315 0000000000000000: f6 ec [P] dontcare %ax (s), %al (u), %ah (u)
1316 f6 / 5 386 OpcodeInModRm OpcodeUsesModRm OperandSize_b Pa rtialInstruction
1317 DontCare %ax, %al, $Eb
1318 RegAX OpSet
1319 RegAL OpUse
1320 E_Operand OpUse
1321 NaClExpVector[6] = {
1322 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1323 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
1324 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1325 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
1326 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1327 { ExprRegister[0] , %ah, ExprUsed | ExprSize8 },
1328 };
1329 0000000000000000: 0f af 91 70 01 00 00 [P] dontcare %edx (suz), [%rcx+0x170] (u)
1330 0f af 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o PartialInstruction
1331 DontCare $Gv, $Ev
1332 G_Operand OpUse OpSet OperandZeroExtends_v
1333 E_Operand OpUse
1334 NaClExpVector[8] = {
1335 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1336 { ExprRegister[0] , %edx, ExprSet | ExprUsed | ExprSize32 },
1337 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1338 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1339 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
1340 { ExprRegister[0] , %unknown, 0 },
1341 { ExprConstant[0] , 1, ExprSize8 },
1342 { ExprConstant[0] , 0x170, ExprSize32 | ExprSignedHex },
1343 };
1344 0000000000000000: 0f af c1 [P] dontcare %eax (suz), %ecx (u)
1345 0f af 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o PartialInstruction
1346 DontCare $Gv, $Ev
1347 G_Operand OpUse OpSet OperandZeroExtends_v
1348 E_Operand OpUse
1349 NaClExpVector[4] = {
1350 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1351 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1352 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1353 { ExprRegister[0] , %ecx, ExprUsed | ExprSize32 },
1354 };
1355 0000000000000000: f6 fc [P] dontcare %ax (s), %al (u), %ah (u)
1356 f6 / 7 386 OpcodeInModRm OpcodeUsesModRm OperandSize_b Pa rtialInstruction
1357 DontCare %ax, %al, $Eb
1358 RegAX OpSet
1359 RegAL OpUse
1360 E_Operand OpUse
1361 NaClExpVector[6] = {
1362 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1363 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
1364 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1365 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
1366 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1367 { ExprRegister[0] , %ah, ExprUsed | ExprSize8 },
1368 };
1369 0000000000000000: f7 f9 [P] dontcare %edx (s), %eax (su), %ecx (u)
1370 f7 / 7 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1371 DontCare %redx, %reax, $Ev
1372 RegREDX OpSet
1373 RegREAX OpUse OpSet
1374 E_Operand OpUse
1375 NaClExpVector[6] = {
1376 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1377 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
1378 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1379 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1380 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1381 { ExprRegister[0] , %ecx, ExprUsed | ExprSize32 },
1382 };
1383 0000000000000000: f7 be 70 01 00 00 [P] dontcare %edx (s), %eax (su), [%rsi+0x170] (u)
1384 f7 / 7 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1385 DontCare %redx, %reax, $Ev
1386 RegREDX OpSet
1387 RegREAX OpUse OpSet
1388 E_Operand OpUse
1389 NaClExpVector[10] = {
1390 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1391 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
1392 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1393 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1394 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1395 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1396 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
1397 { ExprRegister[0] , %unknown, 0 },
1398 { ExprConstant[0] , 1, ExprSize8 },
1399 { ExprConstant[0] , 0x170, ExprSize32 | ExprSignedHex },
1400 };
1401 0000000000000000: 48 f7 f9 [P] dontcare %rdx (s), %rax (su), %rcx (u)
1402 f7 / 7 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1403 DontCare %redx, %reax, $Ev
1404 RegREDX OpSet
1405 RegREAX OpUse OpSet
1406 E_Operand OpUse
1407 NaClExpVector[6] = {
1408 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1409 { ExprRegister[0] , %rdx, ExprSet | ExprSize64 },
1410 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1411 { ExprRegister[0] , %rax, ExprSet | ExprUsed | ExprSize64 },
1412 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1413 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
1414 };
1415 0000000000000000: fc [P] dontcare
1416 fc 386 PartialInstruction
1417 DontCare
1418 NaClExpVector[0] = {
1419 };
1420 0000000000000000: f6 d8 [P] dontcare %al (su)
1421 f6 / 3 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b PartialInstruction
1422 DontCare $Eb
1423 E_Operand OpUse OpSet
1424 NaClExpVector[2] = {
1425 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1426 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
1427 };
1428 0000000000000000: f7 d9 [P] dontcare %ecx (suz)
1429 f7 / 3 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1430 DontCare $Ev
1431 E_Operand OpUse OpSet OperandZeroExtends_v
1432 NaClExpVector[2] = {
1433 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1434 { ExprRegister[0] , %ecx, ExprSet | ExprUsed | ExprSize32 },
1435 };
1436 0000000000000000: 49 f7 de [P] dontcare %r14 (suz)
1437 f7 / 3 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1438 DontCare $Ev
1439 E_Operand OpUse OpSet OperandZeroExtends_v
1440 NaClExpVector[2] = {
1441 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1442 { ExprRegister[0] , %r14, ExprSet | ExprUsed | ExprSize64 },
1443 };
1444 0000000000000000: 48 f7 da [P] dontcare %rdx (suz)
1445 f7 / 3 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1446 DontCare $Ev
1447 E_Operand OpUse OpSet OperandZeroExtends_v
1448 NaClExpVector[2] = {
1449 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1450 { ExprRegister[0] , %rdx, ExprSet | ExprUsed | ExprSize64 },
1451 };
1452 0000000000000000: f6 d1 [P] dontcare %cl (su)
1453 f6 / 2 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b PartialInstruction
1454 DontCare $Eb
1455 E_Operand OpUse OpSet
1456 NaClExpVector[2] = {
1457 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1458 { ExprRegister[0] , %cl, ExprSet | ExprUsed | ExprSize8 },
1459 };
1460 0000000000000000: f7 d1 [P] dontcare %ecx (suz)
1461 f7 / 2 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1462 DontCare $Ev
1463 E_Operand OpUse OpSet OperandZeroExtends_v
1464 NaClExpVector[2] = {
1465 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1466 { ExprRegister[0] , %ecx, ExprSet | ExprUsed | ExprSize32 },
1467 };
1468 0000000000000000: 48 f7 d2 [P] dontcare %rdx (suz)
1469 f7 / 2 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1470 DontCare $Ev
1471 E_Operand OpUse OpSet OperandZeroExtends_v
1472 NaClExpVector[2] = {
1473 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1474 { ExprRegister[0] , %rdx, ExprSet | ExprUsed | ExprSize64 },
1475 };
1476 0000000000000000: f6 e2 [P] dontcare %ax (s), %al (u), %dl (u)
1477 f6 / 4 386 OpcodeInModRm OpcodeUsesModRm OperandSize_b Pa rtialInstruction
1478 DontCare %ax, %al, $Eb
1479 RegAX OpSet
1480 RegAL OpUse
1481 E_Operand OpUse
1482 NaClExpVector[6] = {
1483 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1484 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
1485 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1486 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
1487 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1488 { ExprRegister[0] , %dl, ExprUsed | ExprSize8 },
1489 };
1490 0000000000000000: f7 e2 [P] dontcare %edx (s), %eax (su), %edx (u)
1491 f7 / 4 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1492 DontCare %redx, %reax, $Ev
1493 RegREDX OpSet
1494 RegREAX OpUse OpSet
1495 E_Operand OpUse
1496 NaClExpVector[6] = {
1497 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1498 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
1499 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1500 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1501 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1502 { ExprRegister[0] , %edx, ExprUsed | ExprSize32 },
1503 };
1504 0000000000000000: 48 f7 e7 [P] dontcare %rdx (s), %rax (su), %rdi (u)
1505 f7 / 4 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1506 DontCare %redx, %reax, $Ev
1507 RegREDX OpSet
1508 RegREAX OpUse OpSet
1509 E_Operand OpUse
1510 NaClExpVector[6] = {
1511 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1512 { ExprRegister[0] , %rdx, ExprSet | ExprSize64 },
1513 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1514 { ExprRegister[0] , %rax, ExprSet | ExprUsed | ExprSize64 },
1515 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1516 { ExprRegister[0] , %rdi, ExprUsed | ExprSize64 },
1517 };
1518 0000000000000000: 41 f7 e6 [P] dontcare %edx (s), %eax (su), %r14d (u)
1519 f7 / 4 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1520 DontCare %redx, %reax, $Ev
1521 RegREDX OpSet
1522 RegREAX OpUse OpSet
1523 E_Operand OpUse
1524 NaClExpVector[6] = {
1525 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1526 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
1527 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1528 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1529 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1530 { ExprRegister[0] , %r14d, ExprUsed | ExprSize32 },
1531 };
1532 0000000000000000: 48 f7 f1 [P] dontcare %rdx (s), %rax (su), %rcx (u)
1533 f7 / 6 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1534 DontCare %redx, %reax, $Ev
1535 RegREDX OpSet
1536 RegREAX OpUse OpSet
1537 E_Operand OpUse
1538 NaClExpVector[6] = {
1539 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1540 { ExprRegister[0] , %rdx, ExprSet | ExprSize64 },
1541 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1542 { ExprRegister[0] , %rax, ExprSet | ExprUsed | ExprSize64 },
1543 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1544 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
1545 };
1546 0000000000000000: 48 f7 71 38 [P] dontcare %rdx (s), %rax (su), [%rcx+0x38] (u)
1547 f7 / 6 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1548 DontCare %redx, %reax, $Ev
1549 RegREDX OpSet
1550 RegREAX OpUse OpSet
1551 E_Operand OpUse
1552 NaClExpVector[10] = {
1553 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1554 { ExprRegister[0] , %rdx, ExprSet | ExprSize64 },
1555 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1556 { ExprRegister[0] , %rax, ExprSet | ExprUsed | ExprSize64 },
1557 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1558 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1559 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
1560 { ExprRegister[0] , %unknown, 0 },
1561 { ExprConstant[0] , 1, ExprSize8 },
1562 { ExprConstant[0] , 0x38, ExprSize8 | ExprSignedHex },
1563 };
1564 0000000000000000: f7 35 37 af 57 00 [P] dontcare %edx (s), %eax (su), [%rip+0x57af37] (u)
1565 f7 / 6 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1566 DontCare %redx, %reax, $Ev
1567 RegREDX OpSet
1568 RegREAX OpUse OpSet
1569 E_Operand OpUse
1570 NaClExpVector[10] = {
1571 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1572 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
1573 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1574 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1575 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1576 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1577 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
1578 { ExprRegister[0] , %unknown, 0 },
1579 { ExprConstant[0] , 1, ExprSize8 },
1580 { ExprConstant[0] , 0x57af37, ExprSize32 | ExprSignedHex },
1581 };
1582 0000000000000000: f2 0f 10 05 b5 dc 15 00 [P] dontcare [%ri p+0x15dcb5] (u)
1583 f2 0f 10 SSE2 OpcodeUsesModRm OpcodeAllowsRepne PartialInst ruction
1584 DontCare $Wsd
1585 Xmm_E_Operand OpUse
1586 NaClExpVector[6] = {
1587 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1588 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1589 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
1590 { ExprRegister[0] , %unknown, 0 },
1591 { ExprConstant[0] , 1, ExprSize8 },
1592 { ExprConstant[0] , 0x15dcb5, ExprSize32 | ExprSignedHex },
1593 };
1594 0000000000000000: f2 0f 11 54 24 10 [P] dontcare [%rs p+0x10] (s)
1595 f2 0f 11 SSE2 OpcodeUsesModRm OpcodeAllowsRepne PartialInst ruction
1596 DontCare $Wsd
1597 Xmm_E_Operand OpSet
1598 NaClExpVector[6] = {
1599 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1600 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
1601 { ExprRegister[0] , %rsp, ExprUsed | ExprSize64 },
1602 { ExprRegister[0] , %unknown, 0 },
1603 { ExprConstant[0] , 1, ExprSize8 },
1604 { ExprConstant[0] , 0x10, ExprSize8 | ExprSignedHex },
1605 };
1606 0000000000000000: f3 0f 10 02 [P] dontcare [%rd x] (u)
1607 f3 0f 10 SSE OpcodeUsesModRm OpcodeAllowsRep PartialInstruc tion
1608 DontCare $Wss
1609 Xmm_E_Operand OpUse
1610 NaClExpVector[6] = {
1611 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1612 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1613 { ExprRegister[0] , %rdx, ExprUsed | ExprSize64 },
1614 { ExprRegister[0] , %unknown, 0 },
1615 { ExprConstant[0] , 1, ExprSize8 },
1616 { ExprConstant[0] , 0, ExprSize8 },
1617 };
1618 0000000000000000: f3 0f 11 44 24 0c [P] dontcare [%rs p+0xc] (s)
1619 f3 0f 11 SSE OpcodeUsesModRm OpcodeAllowsRep PartialInstruc tion
1620 DontCare $Wss
1621 Xmm_E_Operand OpSet
1622 NaClExpVector[6] = {
1623 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1624 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
1625 { ExprRegister[0] , %rsp, ExprUsed | ExprSize64 },
1626 { ExprRegister[0] , %unknown, 0 },
1627 { ExprConstant[0] , 1, ExprSize8 },
1628 { ExprConstant[0] , 0xc, ExprSize8 | ExprSignedHex },
1629 };
1630 0000000000000000: f3 0f 10 4c 24 1c [P] dontcare [%rs p+0x1c] (u)
1631 f3 0f 10 SSE OpcodeUsesModRm OpcodeAllowsRep PartialInstruc tion
1632 DontCare $Wss
1633 Xmm_E_Operand OpUse
1634 NaClExpVector[6] = {
1635 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1636 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1637 { ExprRegister[0] , %rsp, ExprUsed | ExprSize64 },
1638 { ExprRegister[0] , %unknown, 0 },
1639 { ExprConstant[0] , 1, ExprSize8 },
1640 { ExprConstant[0] , 0x1c, ExprSize8 | ExprSignedHex },
1641 };
1642 0000000000000000: f3 0f 11 44 24 0c [P] dontcare [%rs p+0xc] (s)
1643 f3 0f 11 SSE OpcodeUsesModRm OpcodeAllowsRep PartialInstruc tion
1644 DontCare $Wss
1645 Xmm_E_Operand OpSet
1646 NaClExpVector[6] = {
1647 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1648 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
1649 { ExprRegister[0] , %rsp, ExprUsed | ExprSize64 },
1650 { ExprRegister[0] , %unknown, 0 },
1651 { ExprConstant[0] , 1, ExprSize8 },
1652 { ExprConstant[0] , 0xc, ExprSize8 | ExprSignedHex },
1653 };
1654 0000000000000000: f2 0f 5f cf [P] dontcare %xmm 7 (u)
1655 f2 0f 5f SSE2 OpcodeUsesModRm OpcodeAllowsRepne PartialInst ruction
1656 DontCare $Wsd
1657 Xmm_E_Operand OpUse
1658 NaClExpVector[2] = {
1659 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1660 { ExprRegister[0] , %xmm7, ExprUsed },
1661 };
1662 0000000000000000: 0f c8 [P] dontcare %eax (su)
1663 0f c8 - r0 386 OpcodePlusR OperandSize_v PartialInstruction
1664 DontCare $r8vd
1665 G_OpcodeBase OpUse OpSet
1666 NaClExpVector[2] = {
1667 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1668 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1669 };
1670 0000000000000000: 48 0f c8 [P] dontcare %rax (su)
1671 0f c8 - r0 386 OpcodePlusR OperandSize_o PartialInstruction
1672 DontCare $r8vq
1673 G_OpcodeBase OpUse OpSet
1674 NaClExpVector[2] = {
1675 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1676 { ExprRegister[0] , %rax, ExprSet | ExprUsed | ExprSize64 },
1677 };
1678 0000000000000000: 49 0f cd [P] dontcare %r13 (su)
1679 0f cd - r5 386 OpcodePlusR OperandSize_o PartialInstruction
1680 DontCare $r8vq
1681 G_OpcodeBase OpUse OpSet
1682 NaClExpVector[2] = {
1683 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1684 { ExprRegister[0] , %r13, ExprSet | ExprUsed | ExprSize64 },
1685 };
1686 0000000000000000: 0f 6e 11 [P] dontcare [%rc x] (u)
1687 0f 6e MMX OpcodeUsesModRm SizeIgnoresData16 OperandSize_ v PartialInstruction
1688 DontCare $Ed/q/d
1689 E_Operand OpUse
1690 NaClExpVector[6] = {
1691 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1692 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1693 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
1694 { ExprRegister[0] , %unknown, 0 },
1695 { ExprConstant[0] , 1, ExprSize8 },
1696 { ExprConstant[0] , 0, ExprSize8 },
1697 };
1698 0000000000000000: 49 0f 6e 11 [P] dontcare [%r9 ] (u)
1699 0f 6e MMX OpcodeUsesModRm SizeIgnoresData16 OperandSize_ o PartialInstruction
1700 DontCare $Ed/q/q
1701 E_Operand OpUse
1702 NaClExpVector[6] = {
1703 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1704 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1705 { ExprRegister[0] , %r9, ExprUsed | ExprSize64 },
1706 { ExprRegister[0] , %unknown, 0 },
1707 { ExprConstant[0] , 1, ExprSize8 },
1708 { ExprConstant[0] , 0, ExprSize8 },
1709 };
1710 0000000000000000: 66 0f 6e 11 [P] dontcare [%rc x] (u)
1711 66 0f 6e SSE2 OpcodeUsesModRm OpcodeAllowsData16 SizeIgnore sData16 OperandSize_v PartialInstruction
1712 DontCare $Ed/q/d
1713 E_Operand OpUse
1714 NaClExpVector[6] = {
1715 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1716 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1717 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
1718 { ExprRegister[0] , %unknown, 0 },
1719 { ExprConstant[0] , 1, ExprSize8 },
1720 { ExprConstant[0] , 0, ExprSize8 },
1721 };
1722 0000000000000000: 0f 7e 0e [P] dontcare [%rs i] (sz)
1723 0f 7e MMX OpcodeUsesModRm SizeIgnoresData16 OperandSize_ v PartialInstruction
1724 DontCare $Ed/q/d
1725 E_Operand OpSet OperandZeroExtends_v
1726 NaClExpVector[6] = {
1727 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1728 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
1729 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
1730 { ExprRegister[0] , %unknown, 0 },
1731 { ExprConstant[0] , 1, ExprSize8 },
1732 { ExprConstant[0] , 0, ExprSize8 },
1733 };
1734 0000000000000000: 49 0f 7e 0e [P] dontcare [%r1 4] (s)
1735 0f 7e MMX OpcodeUsesModRm SizeIgnoresData16 OperandSize_ o PartialInstruction
1736 DontCare $Ed/q/q
1737 E_Operand OpSet
1738 NaClExpVector[6] = {
1739 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1740 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
1741 { ExprRegister[0] , %r14, ExprUsed | ExprSize64 },
1742 { ExprRegister[0] , %unknown, 0 },
1743 { ExprConstant[0] , 1, ExprSize8 },
1744 { ExprConstant[0] , 0, ExprSize8 },
1745 };
1746 0000000000000000: 0f 77 [P] dontcare
1747 0f 77 MMX PartialInstruction
1748 DontCare
1749 NaClExpVector[0] = {
1750 };
1751 0000000000000000: f2 0f c2 c7 01 [P] dontcare %xmm 7 (u), 0x1 (u)
1752 f2 0f c2 SSE2 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllows Repne PartialInstruction
1753 DontCare $Wsd, $Ib
1754 Xmm_E_Operand OpUse
1755 I_Operand OpUse
1756 NaClExpVector[4] = {
1757 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1758 { ExprRegister[0] , %xmm7, ExprUsed },
1759 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1760 { ExprConstant[0] , 0x1, ExprUsed | ExprSize8 | ExprUnsignedHex },
1761 };
1762 0000000000000000: f2 0f c2 0d 67 87 10 00 05 [P] dontcare [%ri p+0x108767] (u), 0x5 (u)
1763 f2 0f c2 SSE2 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllows Repne PartialInstruction
1764 DontCare $Wsd, $Ib
1765 Xmm_E_Operand OpUse
1766 I_Operand OpUse
1767 NaClExpVector[8] = {
1768 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1769 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1770 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
1771 { ExprRegister[0] , %unknown, 0 },
1772 { ExprConstant[0] , 1, ExprSize8 },
1773 { ExprConstant[0] , 0x108767, ExprSize32 | ExprSignedHex },
1774 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1775 { ExprConstant[0] , 0x5, ExprUsed | ExprSize8 | ExprUnsignedHex },
1776 };
1777 0000000000000000: f3 0f c2 c7 01 [P] dontcare %xmm 7 (u), 0x1 (u)
1778 f3 0f c2 SSE OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsR ep PartialInstruction
1779 DontCare $Wss, $Ib
1780 Xmm_E_Operand OpUse
1781 I_Operand OpUse
1782 NaClExpVector[4] = {
1783 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1784 { ExprRegister[0] , %xmm7, ExprUsed },
1785 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1786 { ExprConstant[0] , 0x1, ExprUsed | ExprSize8 | ExprUnsignedHex },
1787 };
1788 0000000000000000: f3 0f c2 0d 67 87 10 00 05 [P] dontcare [%ri p+0x108767] (u), 0x5 (u)
1789 f3 0f c2 SSE OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsR ep PartialInstruction
1790 DontCare $Wss, $Ib
1791 Xmm_E_Operand OpUse
1792 I_Operand OpUse
1793 NaClExpVector[8] = {
1794 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1795 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1796 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
1797 { ExprRegister[0] , %unknown, 0 },
1798 { ExprConstant[0] , 1, ExprSize8 },
1799 { ExprConstant[0] , 0x108767, ExprSize32 | ExprSignedHex },
1800 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1801 { ExprConstant[0] , 0x5, ExprUsed | ExprSize8 | ExprUnsignedHex },
1802 };
1803 0000000000000000: 0f 6f 05 ba 87 0f 00 [P] dontcare [%ri p+0xf87ba] (u)
1804 0f 6f MMX OpcodeUsesModRm PartialInstruction
1805 DontCare $Qq
1806 Mmx_E_Operand OpUse
1807 NaClExpVector[6] = {
1808 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1809 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1810 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
1811 { ExprRegister[0] , %unknown, 0 },
1812 { ExprConstant[0] , 1, ExprSize8 },
1813 { ExprConstant[0] , 0xf87ba, ExprSize32 | ExprSignedHex },
1814 };
1815 0000000000000000: 0f 6f c8 [P] dontcare %mmx 0 (u)
1816 0f 6f MMX OpcodeUsesModRm PartialInstruction
1817 DontCare $Qq
1818 Mmx_E_Operand OpUse
1819 NaClExpVector[2] = {
1820 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1821 { ExprRegister[0] , %mmx0, ExprUsed },
1822 };
1823 0000000000000000: 0f 7f 0e [P] dontcare [%rs i] (s)
1824 0f 7f MMX OpcodeUsesModRm PartialInstruction
1825 DontCare $Qq
1826 Mmx_E_Operand OpSet
1827 NaClExpVector[6] = {
1828 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1829 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
1830 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
1831 { ExprRegister[0] , %unknown, 0 },
1832 { ExprConstant[0] , 1, ExprSize8 },
1833 { ExprConstant[0] , 0, ExprSize8 },
1834 };
1835 0000000000000000: 0f d1 0c 25 08 00 00 00 [P] dontcare [0x8 ] (u)
1836 0f d1 MMX OpcodeUsesModRm PartialInstruction
1837 DontCare $Qq
1838 Mmx_E_Operand OpUse
1839 NaClExpVector[6] = {
1840 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1841 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1842 { ExprRegister[0] , %unknown, 0 },
1843 { ExprRegister[0] , %unknown, 0 },
1844 { ExprConstant[0] , 1, ExprSize8 },
1845 { ExprConstant[0] , 0x8, ExprSize32 | ExprSignedHex },
1846 };
1847 0000000000000000: 0f 71 d1 08 [P] dontcare %mmx 1 (su), 0x8 (u)
1848 0f 71 / 2 MMX OpcodeInModRm ModRmModIs0x3 OpcodeUsesModRm Op codeHasImmed_b PartialInstruction
1849 DontCare $PRq, $Ib
1850 Mmx_E_Operand OpUse OpSet
1851 I_Operand OpUse
1852 NaClExpVector[4] = {
1853 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1854 { ExprRegister[0] , %mmx1, ExprSet | ExprUsed },
1855 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1856 { ExprConstant[0] , 0x8, ExprUsed | ExprSize8 | ExprUnsignedHex },
1857 };
1858 0000000000000000: 0f 6e e8 [P] dontcare %eax (u)
1859 0f 6e MMX OpcodeUsesModRm SizeIgnoresData16 OperandSize_ v PartialInstruction
1860 DontCare $Ed/q/d
1861 E_Operand OpUse
1862 NaClExpVector[2] = {
1863 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1864 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
1865 };
1866 0000000000000000: f3 0f 6f 05 f9 77 0f 00 [P] dontcare [%ri p+0xf77f9] (u)
1867 f3 0f 6f SSE2 OpcodeUsesModRm OpcodeAllowsRep PartialInstru ction
1868 DontCare $Wdq
1869 Xmm_E_Operand OpUse
1870 NaClExpVector[6] = {
1871 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1872 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1873 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
1874 { ExprRegister[0] , %unknown, 0 },
1875 { ExprConstant[0] , 1, ExprSize8 },
1876 { ExprConstant[0] , 0xf77f9, ExprSize32 | ExprSignedHex },
1877 };
1878 0000000000000000: f3 0f 6f 11 [P] dontcare [%rc x] (u)
1879 f3 0f 6f SSE2 OpcodeUsesModRm OpcodeAllowsRep PartialInstru ction
1880 DontCare $Wdq
1881 Xmm_E_Operand OpUse
1882 NaClExpVector[6] = {
1883 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1884 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1885 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
1886 { ExprRegister[0] , %unknown, 0 },
1887 { ExprConstant[0] , 1, ExprSize8 },
1888 { ExprConstant[0] , 0, ExprSize8 },
1889 };
1890 0000000000000000: f3 0f 7f 0e [P] dontcare [%rs i] (s)
1891 f3 0f 7f SSE2 OpcodeUsesModRm OpcodeAllowsRep PartialInstru ction
1892 DontCare $Wdq
1893 Xmm_E_Operand OpSet
1894 NaClExpVector[6] = {
1895 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1896 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
1897 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
1898 { ExprRegister[0] , %unknown, 0 },
1899 { ExprConstant[0] , 1, ExprSize8 },
1900 { ExprConstant[0] , 0, ExprSize8 },
1901 };
1902 0000000000000000: 0f e7 0e [P] dontcare [%rs i] (s)
1903 0f e7 MMX ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruc tion
1904 DontCare $Mq
1905 Mo_Operand OpSet
1906 NaClExpVector[6] = {
1907 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1908 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
1909 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
1910 { ExprRegister[0] , %unknown, 0 },
1911 { ExprConstant[0] , 1, ExprSize8 },
1912 { ExprConstant[0] , 0, ExprSize8 },
1913 };
1914 0000000000000000: 66 0f 29 0c 24 [P] dontcare [%rs p] (s)
1915 66 0f 29 SSE2 OpcodeUsesModRm OpcodeAllowsData16 SizeIgnore sData16 PartialInstruction
1916 DontCare $Wpd
1917 Xmm_E_Operand OpSet
1918 NaClExpVector[6] = {
1919 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1920 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
1921 { ExprRegister[0] , %rsp, ExprUsed | ExprSize64 },
1922 { ExprRegister[0] , %unknown, 0 },
1923 { ExprConstant[0] , 1, ExprSize8 },
1924 { ExprConstant[0] , 0, ExprSize8 },
1925 };
1926 0000000000000000: f3 0f 51 d0 [P] dontcare %xmm 0 (u)
1927 f3 0f 51 SSE OpcodeUsesModRm OpcodeAllowsRep PartialInstruc tion
1928 DontCare $Wps
1929 Xmm_E_Operand OpUse
1930 NaClExpVector[2] = {
1931 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1932 { ExprRegister[0] , %xmm0, ExprUsed },
1933 };
1934 0000000000000000: 48 ff c0 [P] dontcare %rax (suz)
1935 ff / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1936 DontCare $Ev
1937 E_Operand OpUse OpSet OperandZeroExtends_v
1938 NaClExpVector[2] = {
1939 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1940 { ExprRegister[0] , %rax, ExprSet | ExprUsed | ExprSize64 },
1941 };
1942 0000000000000000: ff 05 a4 76 39 00 [P] dontcare [%ri p+0x3976a4] (suz)
1943 ff / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1944 DontCare $Ev
1945 E_Operand OpUse OpSet OperandZeroExtends_v
1946 NaClExpVector[6] = {
1947 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1948 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
1949 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
1950 { ExprRegister[0] , %unknown, 0 },
1951 { ExprConstant[0] , 1, ExprSize8 },
1952 { ExprConstant[0] , 0x3976a4, ExprSize32 | ExprSignedHex },
1953 };
1954 0000000000000000: ff c0 [P] dontcare %eax (suz)
1955 ff / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1956 DontCare $Ev
1957 E_Operand OpUse OpSet OperandZeroExtends_v
1958 NaClExpVector[2] = {
1959 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1960 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1961 };
1962 0000000000000000: 41 ff c5 [P] dontcare %r13 d (suz)
1963 ff / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1964 DontCare $Ev
1965 E_Operand OpUse OpSet OperandZeroExtends_v
1966 NaClExpVector[2] = {
1967 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1968 { ExprRegister[0] , %r13d, ExprSet | ExprUsed | ExprSize32 },
1969 };
1970 0000000000000000: fe c0 [P] dontcare %al (su)
1971 fe / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b PartialInstruction
1972 DontCare $Eb
1973 E_Operand OpUse OpSet
1974 NaClExpVector[2] = {
1975 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1976 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
1977 };
1978 0000000000000000: fe c4 [P] dontcare %ah (su)
1979 fe / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b PartialInstruction
1980 DontCare $Eb
1981 E_Operand OpUse OpSet
1982 NaClExpVector[2] = {
1983 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1984 { ExprRegister[0] , %ah, ExprSet | ExprUsed | ExprSize8 },
1985 };
1986 0000000000000000: 41 fe c0 [P] dontcare %r8b (su)
1987 fe / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b PartialInstruction
1988 DontCare $Eb
1989 E_Operand OpUse OpSet
1990 NaClExpVector[2] = {
1991 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1992 { ExprRegister[0] , %r8b, ExprSet | ExprUsed | ExprSize8 },
1993 };
1994 0000000000000000: ff ca [P] dontcare %edx (suz)
1995 ff / 1 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
1996 DontCare $Ev
1997 E_Operand OpUse OpSet OperandZeroExtends_v
1998 NaClExpVector[2] = {
1999 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2000 { ExprRegister[0] , %edx, ExprSet | ExprUsed | ExprSize32 },
2001 };
2002 0000000000000000: ff 0d 8f 76 39 00 [P] dontcare [%ri p+0x39768f] (suz)
2003 ff / 1 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
2004 DontCare $Ev
2005 E_Operand OpUse OpSet OperandZeroExtends_v
2006 NaClExpVector[6] = {
2007 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2008 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2009 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
2010 { ExprRegister[0] , %unknown, 0 },
2011 { ExprConstant[0] , 1, ExprSize8 },
2012 { ExprConstant[0] , 0x39768f, ExprSize32 | ExprSignedHex },
2013 };
2014 0000000000000000: 48 ff c8 [P] dontcare %rax (suz)
2015 ff / 1 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
2016 DontCare $Ev
2017 E_Operand OpUse OpSet OperandZeroExtends_v
2018 NaClExpVector[2] = {
2019 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2020 { ExprRegister[0] , %rax, ExprSet | ExprUsed | ExprSize64 },
2021 };
2022 0000000000000000: 49 ff cc [P] dontcare %r12 (suz)
2023 ff / 1 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
2024 DontCare $Ev
2025 E_Operand OpUse OpSet OperandZeroExtends_v
2026 NaClExpVector[2] = {
2027 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2028 { ExprRegister[0] , %r12, ExprSet | ExprUsed | ExprSize64 },
2029 };
2030 0000000000000000: fe c8 [P] dontcare %al (su)
2031 fe / 1 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b PartialInstruction
2032 DontCare $Eb
2033 E_Operand OpUse OpSet
2034 NaClExpVector[2] = {
2035 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2036 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
2037 };
2038 0000000000000000: fe cc [P] dontcare %ah (su)
2039 fe / 1 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b PartialInstruction
2040 DontCare $Eb
2041 E_Operand OpUse OpSet
2042 NaClExpVector[2] = {
2043 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2044 { ExprRegister[0] , %ah, ExprSet | ExprUsed | ExprSize8 },
2045 };
2046 0000000000000000: 41 fe c8 [P] dontcare %r8b (su)
2047 fe / 1 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b PartialInstruction
2048 DontCare $Eb
2049 E_Operand OpUse OpSet
2050 NaClExpVector[2] = {
2051 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2052 { ExprRegister[0] , %r8b, ExprSet | ExprUsed | ExprSize8 },
2053 };
2054 0000000000000000: f0 0f b1 35 21 c6 31 00 [P] dontcare %eax (su), [%rip+0x31c621] (su), %esi (su)
2055 0f b1 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
2056 DontCare $rAXv, $Ev, $Gv
2057 RegREAX OpUse OpSet
2058 E_Operand OpUse OpSet
2059 G_Operand OpUse OpSet
2060 NaClExpVector[10] = {
2061 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2062 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
2063 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2064 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2065 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
2066 { ExprRegister[0] , %unknown, 0 },
2067 { ExprConstant[0] , 1, ExprSize8 },
2068 { ExprConstant[0] , 0x31c621, ExprSize32 | ExprSignedHex },
2069 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2070 { ExprRegister[0] , %esi, ExprSet | ExprUsed | ExprSize32 },
2071 };
2072 0000000000000000: 0f b1 35 12 c6 31 00 [P] dontcare %eax (su), [%rip+0x31c612] (su), %esi (su)
2073 0f b1 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
2074 DontCare $rAXv, $Ev, $Gv
2075 RegREAX OpUse OpSet
2076 E_Operand OpUse OpSet
2077 G_Operand OpUse OpSet
2078 NaClExpVector[10] = {
2079 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2080 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
2081 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2082 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2083 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
2084 { ExprRegister[0] , %unknown, 0 },
2085 { ExprConstant[0] , 1, ExprSize8 },
2086 { ExprConstant[0] , 0x31c612, ExprSize32 | ExprSignedHex },
2087 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2088 { ExprRegister[0] , %esi, ExprSet | ExprUsed | ExprSize32 },
2089 };
2090 0000000000000000: f0 41 0f b1 30 [P] dontcare %eax (su), [%r8] (su), %esi (su)
2091 0f b1 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
2092 DontCare $rAXv, $Ev, $Gv
2093 RegREAX OpUse OpSet
2094 E_Operand OpUse OpSet
2095 G_Operand OpUse OpSet
2096 NaClExpVector[10] = {
2097 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2098 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
2099 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2100 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2101 { ExprRegister[0] , %r8, ExprUsed | ExprSize64 },
2102 { ExprRegister[0] , %unknown, 0 },
2103 { ExprConstant[0] , 1, ExprSize8 },
2104 { ExprConstant[0] , 0, ExprSize8 },
2105 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2106 { ExprRegister[0] , %esi, ExprSet | ExprUsed | ExprSize32 },
2107 };
2108 0000000000000000: f0 0f c1 02 [P] dontcare [%rd x] (suz), %eax (suz)
2109 0f c1 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
2110 DontCare $Ev, $Gv
2111 E_Operand OpUse OpSet OperandZeroExtends_v
2112 G_Operand OpUse OpSet OperandZeroExtends_v
2113 NaClExpVector[8] = {
2114 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2115 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2116 { ExprRegister[0] , %rdx, ExprUsed | ExprSize64 },
2117 { ExprRegister[0] , %unknown, 0 },
2118 { ExprConstant[0] , 1, ExprSize8 },
2119 { ExprConstant[0] , 0, ExprSize8 },
2120 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2121 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
2122 };
2123 0000000000000000: f0 0f c1 43 18 [P] dontcare [%rb x+0x18] (suz), %eax (suz)
2124 0f c1 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
2125 DontCare $Ev, $Gv
2126 E_Operand OpUse OpSet OperandZeroExtends_v
2127 G_Operand OpUse OpSet OperandZeroExtends_v
2128 NaClExpVector[8] = {
2129 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2130 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2131 { ExprRegister[0] , %rbx, ExprUsed | ExprSize64 },
2132 { ExprRegister[0] , %unknown, 0 },
2133 { ExprConstant[0] , 1, ExprSize8 },
2134 { ExprConstant[0] , 0x18, ExprSize8 | ExprSignedHex },
2135 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2136 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
2137 };
2138 0000000000000000: f0 41 0f c1 00 [P] dontcare [%r8 ] (suz), %eax (suz)
2139 0f c1 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
2140 DontCare $Ev, $Gv
2141 E_Operand OpUse OpSet OperandZeroExtends_v
2142 G_Operand OpUse OpSet OperandZeroExtends_v
2143 NaClExpVector[8] = {
2144 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2145 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2146 { ExprRegister[0] , %r8, ExprUsed | ExprSize64 },
2147 { ExprRegister[0] , %unknown, 0 },
2148 { ExprConstant[0] , 1, ExprSize8 },
2149 { ExprConstant[0] , 0, ExprSize8 },
2150 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2151 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
2152 };
2153 0000000000000000: 0f 05 [P] dontcare(ille gal)
2154 0f 05 SYSCALL NaClIllegal PartialInstruction
2155 DontCare
2156 NaClExpVector[0] = {
2157 };
2158 0000000000000000: e4 08 [P] dontcare(ille gal)
2159 e4 386 OpcodeHasImmed_b NaClIllegal PartialInstructio n
2160 DontCare
2161 NaClExpVector[0] = {
2162 };
2163 0000000000000000: 66 e5 08 [P] dontcare(ille gal)
2164 e5 386 OpcodeHasImmed_b OpcodeAllowsData16 OperandSiz e_w OperandSize_v OperandSize_o NaClIllegal PartialInstruction
2165 DontCare
2166 NaClExpVector[0] = {
2167 };
2168 0000000000000000: e5 08 [P] dontcare(ille gal)
2169 e5 386 OpcodeHasImmed_b OpcodeAllowsData16 OperandSiz e_w OperandSize_v OperandSize_o NaClIllegal PartialInstruction
2170 DontCare
2171 NaClExpVector[0] = {
2172 };
2173 0000000000000000: ec [P] dontcare(ille gal)
2174 ec 386 NaClIllegal PartialInstruction
2175 DontCare
2176 NaClExpVector[0] = {
2177 };
2178 0000000000000000: 66 ed [P] dontcare(ille gal)
2179 ed 386 OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o NaClIllegal PartialInstruction
2180 DontCare
2181 NaClExpVector[0] = {
2182 };
2183 0000000000000000: ed [P] dontcare(ille gal)
2184 ed 386 OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o NaClIllegal PartialInstruction
2185 DontCare
2186 NaClExpVector[0] = {
2187 };
2188 0000000000000000: 55 push %rbp
2189 55 - r5 386 OpcodePlusR OpcodeAllowsData16 OperandSize_w O perandSize_v OperandSize_o OperandSizeDefaultIs64
2190 Push {%rsp}, $r8v
2191 RegRSP OpUse OpSet OpImplicit
2192 G_OpcodeBase OpUse
2193 NaClExpVector[4] = {
2194 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
2195 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
2196 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2197 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
2198 };
2199 0000000000000000: 0f 18 86 00 03 00 00 [P] dontcare [%rs i+0x300]
2200 0f 18 / 0 MMX OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruction
2201 DontCare $Mb
2202 Mb_Operand
2203 NaClExpVector[6] = {
2204 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2205 { ExprMemOffset[4] , 0, ExprSize64 },
2206 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
2207 { ExprRegister[0] , %unknown, 0 },
2208 { ExprConstant[0] , 1, ExprSize8 },
2209 { ExprConstant[0] , 0x300, ExprSize32 | ExprSignedHex },
2210 };
2211 0000000000000000: 48 0f c3 07 [P] dontcare [%rd i] (s), %rax (u)
2212 0f c3 SSE2 ModRmModIsnt0x3 OpcodeUsesModRm SizeIgnoresDa ta16 OperandSize_v OperandSize_o PartialInstruction
2213 DontCare $Md/q, $Gd/q
2214 M_Operand OpSet
2215 G_Operand OpUse
2216 NaClExpVector[8] = {
2217 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2218 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
2219 { ExprRegister[0] , %rdi, ExprUsed | ExprSize64 },
2220 { ExprRegister[0] , %unknown, 0 },
2221 { ExprConstant[0] , 1, ExprSize8 },
2222 { ExprConstant[0] , 0, ExprSize8 },
2223 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2224 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2225 };
2226 0000000000000000: 0f ae f8 [P] dontcare
2227 0f ae / 7 / 0 SFENCE_CLFLUSH OpcodeInModRm OpcodeInModRmRm ModRm ModIs0x3 OpcodeUsesModRm PartialInstruction
2228 DontCare
2229 NaClExpVector[0] = {
2230 };
2231 0000000000000000: 41 0f a3 c0 [P] dontcare(ille gal)
2232 0f a3 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o NaClIllegal PartialInstruction
2233 DontCare
2234 NaClExpVector[0] = {
2235 };
2236 0000000000000000: 41 db 2c 07 [P] dontcare [%r1 5+%rax*1] (u)
2237 db / 5 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruction
2238 DontCare $Mf
2239 M_Operand OpUse
2240 NaClExpVector[6] = {
2241 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2242 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2243 { ExprRegister[0] , %r15, ExprUsed | ExprSize64 },
2244 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2245 { ExprConstant[0] , 1, ExprSize8 },
2246 { ExprConstant[0] , 0, ExprSize8 },
2247 };
2248 0000000000000000: dd 04 24 [P] dontcare [%rs p] (u)
2249 dd / 0 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruction
2250 DontCare $Mq
2251 Mo_Operand OpUse
2252 NaClExpVector[6] = {
2253 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2254 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2255 { ExprRegister[0] , %rsp, ExprUsed | ExprSize64 },
2256 { ExprRegister[0] , %unknown, 0 },
2257 { ExprConstant[0] , 1, ExprSize8 },
2258 { ExprConstant[0] , 0, ExprSize8 },
2259 };
2260 0000000000000000: 0f b3 20 [P] dontcare(ille gal)
2261 0f b3 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o NaClIllegal PartialInstruction
2262 DontCare
2263 NaClExpVector[0] = {
2264 };
2265 0000000000000000: 0f a3 20 [P] dontcare(ille gal)
2266 0f a3 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o NaClIllegal PartialInstruction
2267 DontCare
2268 NaClExpVector[0] = {
2269 };
2270 0000000000000000: 0f bb 20 [P] dontcare(ille gal)
2271 0f bb 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o NaClIllegal PartialInstruction
2272 DontCare
2273 NaClExpVector[0] = {
2274 };
2275 0000000000000000: 0f ab 20 [P] dontcare(ille gal)
2276 0f ab 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o NaClIllegal PartialInstruction
2277 DontCare
2278 NaClExpVector[0] = {
2279 };
2280 0000000000000000: 66 0f 78 c1 02 04 [P] dontcare(ille gal)
2281 66 0f 78 / 0 SSE4A OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed _b OpcodeHasImmed2_b OpcodeAllowsData16 SizeIgnoresData16 NaClIllegal PartialIns truction
2282 DontCare
2283 NaClExpVector[0] = {
2284 };
2285 0000000000000000: f2 0f 78 ca 02 04 [P] dontcare %xmm 2 (u), 0x2 (u), 0x4 (u)
2286 f2 0f 78 SSE4A ModRmModIs0x3 OpcodeUsesModRm OpcodeHasImmed _b OpcodeHasImmed2_b OpcodeAllowsRepne PartialInstruction
2287 DontCare $VRq, $Ib, $Ib
2288 Xmm_E_Operand OpUse
2289 I_Operand OpUse
2290 I2_Operand OpUse
2291 NaClExpVector[6] = {
2292 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2293 { ExprRegister[0] , %xmm2, ExprUsed },
2294 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2295 { ExprConstant[0] , 0x2, ExprUsed | ExprSize8 | ExprUnsignedHex },
2296 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2297 { ExprConstant[0] , 0x4, ExprUsed | ExprSize8 | ExprUnsignedHex },
2298 };
2299 0000000000000000: 66 0f 79 ca [P] dontcare %xmm 2 (u)
2300 66 0f 79 SSE4A ModRmModIs0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 SizeIgnoresData16 PartialInstruction
2301 DontCare $VRdq
2302 Xmm_E_Operand OpUse
2303 NaClExpVector[2] = {
2304 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2305 { ExprRegister[0] , %xmm2, ExprUsed },
2306 };
2307 0000000000000000: f2 0f 79 ca [P] dontcare %xmm 2 (u)
2308 f2 0f 79 SSE4A ModRmModIs0x3 OpcodeUsesModRm OpcodeAllowsRe pne PartialInstruction
2309 DontCare $VRdq
2310 Xmm_E_Operand OpUse
2311 NaClExpVector[2] = {
2312 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2313 { ExprRegister[0] , %xmm2, ExprUsed },
2314 };
2315 0000000000000000: e9 00 00 01 02 [P] dontcarejump %rip (s), 0x2010005 (u)
2316 e9 386 OpcodeHasImmed_v OperandSize_v OperandSize_o O perandSizeDefaultIs64 JumpInstruction PartialInstruction
2317 DontCareJump %rip, $Jzd
2318 RegRIP OpSet
2319 J_Operand OpUse OperandNear OperandRelative
2320 NaClExpVector[4] = {
2321 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2322 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
2323 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2324 { ExprConstant[0] , 0x2010005, ExprUsed | ExprSize32 | ExprSignedHex | ExprJum pTarget },
2325 };
2326 0000000000000000: 67 40 a0 00 01 02 03 mov %al, [0x30201 00]
2327 a0 386 OpcodeHasImmed_Addr OperandSize_b
2328 Mov %al, $Ob
2329 RegAL OpSet
2330 O_Operand OpUse
2331 NaClExpVector[8] = {
2332 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2333 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
2334 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2335 { ExprMemOffset[4] , 0, ExprUsed | ExprSize32 },
2336 { ExprRegister[0] , %unknown, 0 },
2337 { ExprRegister[0] , %unknown, 0 },
2338 { ExprConstant[0] , 1, ExprSize8 },
2339 { ExprConstant[0] , 0x3020100, ExprSize32 | ExprUnsignedHex },
2340 };
2341 0000000000000000: 66 0f 3a 60 00 01 [P] dontcare %eax (s), %edx (s), [%rax] (u), 0x1 (u)
2342 66 0f 3a 60 SSE42 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllow sData16 SizeIgnoresData16 OperandSize_v OperandSize_o PartialInstruction
2343 DontCare $rAXv, $rDXv, $Wdq, $Ib
2344 RegREAX OpSet
2345 RegREDX OpSet
2346 Xmm_E_Operand OpUse
2347 I_Operand OpUse
2348 NaClExpVector[12] = {
2349 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2350 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
2351 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2352 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
2353 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2354 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2355 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2356 { ExprRegister[0] , %unknown, 0 },
2357 { ExprConstant[0] , 1, ExprSize8 },
2358 { ExprConstant[0] , 0, ExprSize8 },
2359 { OperandReference[1] , 3, ExprSize8 | ExprUnsignedInt },
2360 { ExprConstant[0] , 0x1, ExprUsed | ExprSize8 | ExprUnsignedHex },
2361 };
2362 0000000000000000: 90 [P] dontcare
2363 [hard coded] 386 PartialInstruction
2364 DontCare
2365 NaClExpVector[0] = {
2366 };
2367 0000000000000000: 66 90 [P] dontcare
2368 [hard coded] 386 PartialInstruction
2369 DontCare
2370 NaClExpVector[0] = {
2371 };
2372 0000000000000000: 66 66 90 [P] dontcare %ax (suz), %ax (suz)
2373 90 - r0 386 OpcodePlusR OpcodeLockable OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
2374 DontCare $r8v, $rAXv
2375 G_OpcodeBase OpUse OpSet OperandZeroExtends_v
2376 RegREAX OpUse OpSet OperandZeroExtends_v
2377 NaClExpVector[4] = {
2378 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2379 { ExprRegister[0] , %ax, ExprSet | ExprUsed | ExprSize16 },
2380 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2381 { ExprRegister[0] , %ax, ExprSet | ExprUsed | ExprSize16 },
2382 };
2383 0000000000000000: 8d 76 00 lea %esi, [%rsi]
2384 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
2385 Lea $Gv, $M
2386 G_Operand OpSet OperandZeroExtends_v
2387 M_Operand OpAddress
2388 NaClExpVector[8] = {
2389 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2390 { ExprRegister[0] , %esi, ExprSet | ExprSize32 },
2391 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2392 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
2393 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
2394 { ExprRegister[0] , %unknown, 0 },
2395 { ExprConstant[0] , 1, ExprSize8 },
2396 { ExprConstant[0] , 0x0, ExprSize8 | ExprSignedHex },
2397 };
2398 0000000000000000: 8d 74 26 00 lea %esi, [%rsi]
2399 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
2400 Lea $Gv, $M
2401 G_Operand OpSet OperandZeroExtends_v
2402 M_Operand OpAddress
2403 NaClExpVector[8] = {
2404 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2405 { ExprRegister[0] , %esi, ExprSet | ExprSize32 },
2406 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2407 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
2408 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
2409 { ExprRegister[0] , %unknown, 0 },
2410 { ExprConstant[0] , 1, ExprSize8 },
2411 { ExprConstant[0] , 0x0, ExprSize8 | ExprSignedHex },
2412 };
2413 0000000000000000: 8d b6 00 00 00 00 lea %esi, [%rsi]
2414 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
2415 Lea $Gv, $M
2416 G_Operand OpSet OperandZeroExtends_v
2417 M_Operand OpAddress
2418 NaClExpVector[8] = {
2419 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2420 { ExprRegister[0] , %esi, ExprSet | ExprSize32 },
2421 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2422 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
2423 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
2424 { ExprRegister[0] , %unknown, 0 },
2425 { ExprConstant[0] , 1, ExprSize8 },
2426 { ExprConstant[0] , 0x0, ExprSize32 | ExprSignedHex },
2427 };
2428 0000000000000000: 8d b4 26 00 00 00 00 lea %esi, [%rsi]
2429 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
2430 Lea $Gv, $M
2431 G_Operand OpSet OperandZeroExtends_v
2432 M_Operand OpAddress
2433 NaClExpVector[8] = {
2434 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2435 { ExprRegister[0] , %esi, ExprSet | ExprSize32 },
2436 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2437 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
2438 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
2439 { ExprRegister[0] , %unknown, 0 },
2440 { ExprConstant[0] , 1, ExprSize8 },
2441 { ExprConstant[0] , 0x0, ExprSize32 | ExprSignedHex },
2442 };
2443 0000000000000000: 89 f6 mov %esi, %esi
2444 89 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
2445 Mov $Ev, $Gv
2446 E_Operand OpSet OperandZeroExtends_v
2447 G_Operand OpUse
2448 NaClExpVector[4] = {
2449 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2450 { ExprRegister[0] , %esi, ExprSet | ExprSize32 },
2451 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2452 { ExprRegister[0] , %esi, ExprUsed | ExprSize32 },
2453 };
2454 0000000000000000: 8d bc 27 00 00 00 00 lea %edi, [%rdi]
2455 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
2456 Lea $Gv, $M
2457 G_Operand OpSet OperandZeroExtends_v
2458 M_Operand OpAddress
2459 NaClExpVector[8] = {
2460 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2461 { ExprRegister[0] , %edi, ExprSet | ExprSize32 },
2462 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2463 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
2464 { ExprRegister[0] , %rdi, ExprUsed | ExprSize64 },
2465 { ExprRegister[0] , %unknown, 0 },
2466 { ExprConstant[0] , 1, ExprSize8 },
2467 { ExprConstant[0] , 0x0, ExprSize32 | ExprSignedHex },
2468 };
2469 0000000000000000: 0f 1f 00 [P] dontcare
2470 [hard coded] 386 PartialInstruction
2471 DontCare
2472 NaClExpVector[0] = {
2473 };
2474 0000000000000000: 0f 1f 40 00 [P] dontcare
2475 [hard coded] 386 PartialInstruction
2476 DontCare
2477 NaClExpVector[0] = {
2478 };
2479 0000000000000000: 0f 1f 44 00 00 [P] dontcare
2480 [hard coded] 386 PartialInstruction
2481 DontCare
2482 NaClExpVector[0] = {
2483 };
2484 0000000000000000: 66 0f 1f 44 00 00 [P] dontcare
2485 [hard coded] 386 PartialInstruction
2486 DontCare
2487 NaClExpVector[0] = {
2488 };
2489 0000000000000000: 0f 1f 80 00 00 00 00 [P] dontcare
2490 [hard coded] 386 PartialInstruction
2491 DontCare
2492 NaClExpVector[0] = {
2493 };
2494 0000000000000000: 0f 1f 84 00 00 00 00 00 [P] dontcare
2495 [hard coded] 386 PartialInstruction
2496 DontCare
2497 NaClExpVector[0] = {
2498 };
2499 0000000000000000: 66 0f 1f 84 00 00 00 00 00 [P] dontcare
2500 [hard coded] 386 PartialInstruction
2501 DontCare
2502 NaClExpVector[0] = {
2503 };
2504 0000000000000000: 66 2e 0f 1f 84 00 00 00 00 00 [P] dontcare
2505 [hard coded] 386 PartialInstruction
2506 DontCare
2507 NaClExpVector[0] = {
2508 };
2509 0000000000000000: 66 66 2e 0f 1f 84 00 00 00 00 00 [P] dontcare
2510 [hard coded] 386 PartialInstruction
2511 DontCare
2512 NaClExpVector[0] = {
2513 };
2514 0000000000000000: 66 66 66 2e 0f 1f 84 00 00 00 00 00 [P] dontcare
2515 [hard coded] 386 PartialInstruction
2516 DontCare
2517 NaClExpVector[0] = {
2518 };
2519 0000000000000000: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 [P] dontcare
2520 [hard coded] 386 PartialInstruction
2521 DontCare
2522 NaClExpVector[0] = {
2523 };
2524 0000000000000000: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 [P] dontcare
2525 [hard coded] 386 PartialInstruction
2526 DontCare
2527 NaClExpVector[0] = {
2528 };
2529 0000000000000000: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 [P] dontcare
2530 [hard coded] 386 PartialInstruction
2531 DontCare
2532 NaClExpVector[0] = {
2533 };
2534 0000000000000000: 41 ff 74 3f 20 push [%r15+%rdi*1 +0x20]
2535 ff / 6 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o OperandSizeDefaultIs64
2536 Push {%rsp}, $Ev
2537 RegRSP OpUse OpSet OpImplicit
2538 E_Operand OpUse
2539 NaClExpVector[8] = {
2540 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
2541 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
2542 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2543 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2544 { ExprRegister[0] , %r15, ExprUsed | ExprSize64 },
2545 { ExprRegister[0] , %rdi, ExprUsed | ExprSize64 },
2546 { ExprConstant[0] , 1, ExprSize8 },
2547 { ExprConstant[0] , 0x20, ExprSize8 | ExprSignedHex },
2548 };
2549 0000000000000000: 0f 0b [P] dontcare
2550 [hard coded] 386 PartialInstruction
2551 DontCare
2552 NaClExpVector[0] = {
2553 };
2554 0000000000000000: 0f 70 00 00 [P] dontcare [%ra x] (u), 0x0 (u)
2555 0f 70 MMX OpcodeUsesModRm OpcodeHasImmed_b PartialInstru ction
2556 DontCare $Qq, $Ib
2557 Mmx_E_Operand OpUse
2558 I_Operand OpUse
2559 NaClExpVector[8] = {
2560 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2561 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2562 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2563 { ExprRegister[0] , %unknown, 0 },
2564 { ExprConstant[0] , 1, ExprSize8 },
2565 { ExprConstant[0] , 0, ExprSize8 },
2566 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2567 { ExprConstant[0] , 0x0, ExprUsed | ExprSize8 | ExprUnsignedHex },
2568 };
2569 0000000000000000: 0f ae 38 [P] dontcare(ille gal)
2570 0f ae / 7 SFENCE_CLFLUSH OpcodeInModRm ModRmModIsnt0x3 Opcod eUsesModRm NaClIllegal PartialInstruction
2571 DontCare
2572 NaClExpVector[0] = {
2573 };
2574 0000000000000000: 0f ae fc invalid
2575 0f ae / 7 / 4 INVALID OpcodeInModRm OpcodeInModRmRm ModRmModIs0x 3 OpcodeUsesModRm NaClIllegal
2576 NaClExpVector[0] = {
2577 };
2578 0000000000000000: 40 dc 20 [P] dontcare [%ra x] (u)
2579 dc / 4 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruction
2580 DontCare $Mq
2581 Mo_Operand OpUse
2582 NaClExpVector[6] = {
2583 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2584 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2585 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2586 { ExprRegister[0] , %unknown, 0 },
2587 { ExprConstant[0] , 1, ExprSize8 },
2588 { ExprConstant[0] , 0, ExprSize8 },
2589 };
2590 0000000000000000: 0f ba 20 00 [P] dontcare [%ra x] (u), 0x0 (u)
2591 0f ba / 4 386 OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
2592 DontCare $Ev, $Ib
2593 E_Operand OpUse
2594 I_Operand OpUse
2595 NaClExpVector[8] = {
2596 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2597 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2598 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2599 { ExprRegister[0] , %unknown, 0 },
2600 { ExprConstant[0] , 1, ExprSize8 },
2601 { ExprConstant[0] , 0, ExprSize8 },
2602 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2603 { ExprConstant[0] , 0x0, ExprUsed | ExprSize8 | ExprUnsignedHex },
2604 };
2605 0000000000000000: 66 0f 3a 15 00 00 [P] dontcare [%ra x] (s), 0x0 (u)
2606 66 0f 3a 15 SSE41 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllow sData16 SizeIgnoresData16 PartialInstruction
2607 DontCare $Rd/Mw, $Ib
2608 Ev_Operand OpSet
2609 I_Operand OpUse
2610 NaClExpVector[8] = {
2611 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2612 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
2613 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2614 { ExprRegister[0] , %unknown, 0 },
2615 { ExprConstant[0] , 1, ExprSize8 },
2616 { ExprConstant[0] , 0, ExprSize8 },
2617 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2618 { ExprConstant[0] , 0x0, ExprUsed | ExprSize8 | ExprUnsignedHex },
2619 };
2620 0000000000000000: 0f ec 00 [P] dontcare [%ra x] (u)
2621 0f ec MMX OpcodeUsesModRm PartialInstruction
2622 DontCare $Qq
2623 Mmx_E_Operand OpUse
2624 NaClExpVector[6] = {
2625 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2626 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2627 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2628 { ExprRegister[0] , %unknown, 0 },
2629 { ExprConstant[0] , 1, ExprSize8 },
2630 { ExprConstant[0] , 0, ExprSize8 },
2631 };
2632 0000000000000000: 0f f4 00 [P] dontcare [%ra x] (u)
2633 0f f4 MMX OpcodeUsesModRm PartialInstruction
2634 DontCare $Qq
2635 Mmx_E_Operand OpUse
2636 NaClExpVector[6] = {
2637 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2638 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2639 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2640 { ExprRegister[0] , %unknown, 0 },
2641 { ExprConstant[0] , 1, ExprSize8 },
2642 { ExprConstant[0] , 0, ExprSize8 },
2643 };
2644 0000000000001000: 40 e0 00 [P] dontcarecondj ump %rip (s), %rcx (su), 0x1003 (u)
2645 e0 386 OpcodeHasImmed OperandSize_b AddressSize_o Con ditionalJump PartialInstruction
2646 DontCareCondJump %rip, %rcx, $Jb
2647 RegRIP OpSet
2648 RegRCX OpUse OpSet
2649 J_Operand OpUse OperandNear OperandRelative
2650 NaClExpVector[6] = {
2651 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2652 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
2653 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2654 { ExprRegister[0] , %rcx, ExprSet | ExprUsed | ExprSize64 },
2655 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2656 { ExprConstant[0] , 0x1003, ExprUsed | ExprSize8 | ExprSignedHex | ExprJumpTar get },
2657 };
2658 0000000000000000: 40 e3 00 [P] dontcarecondj ump %rip (s), %rcx (u), 0x3 (u)
2659 e3 386 OpcodeHasImmed OperandSize_b AddressSize_o Con ditionalJump BranchHints PartialInstruction
2660 DontCareCondJump %rip, %rcx, $Jb
2661 RegRIP OpSet
2662 RegRCX OpUse
2663 J_Operand OpUse OperandNear OperandRelative
2664 NaClExpVector[6] = {
2665 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2666 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
2667 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2668 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
2669 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2670 { ExprConstant[0] , 0x3, ExprUsed | ExprSize8 | ExprSignedHex | ExprJumpTarget },
2671 };
2672 0000000000000000: 67 40 e3 00 [P] dontcarecondj ump %rip (s), %ecx (u), 0x4 (u)
2673 e3 386 OpcodeHasImmed OperandSize_b AddressSize_v Con ditionalJump BranchHints PartialInstruction
2674 DontCareCondJump %rip, %ecx, $Jb
2675 RegRIP OpSet
2676 RegECX OpUse
2677 J_Operand OpUse OperandNear OperandRelative
2678 NaClExpVector[6] = {
2679 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2680 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
2681 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2682 { ExprRegister[0] , %ecx, ExprUsed | ExprSize32 },
2683 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2684 { ExprConstant[0] , 0x4, ExprUsed | ExprSize8 | ExprSignedHex | ExprJumpTarget },
2685 };
2686 0000000000000000: 41 d9 f0 [P] dontcare
2687 d9 f0 X87 PartialInstruction
2688 DontCare
2689 NaClExpVector[0] = {
2690 };
2691 0000000000000000: 66 0f 52 invalid
2692 66 0f 52 INVALID OpcodeAllowsData16 SizeIgnoresData16 NaClI llegal
2693 NaClExpVector[0] = {
2694 };
2695 0000000000000000: 66 0f 53 invalid
2696 66 0f 53 INVALID OpcodeAllowsData16 SizeIgnoresData16 NaClI llegal
2697 NaClExpVector[0] = {
2698 };
2699 0000000000000000: f2 0f 52 invalid
2700 f2 0f 52 INVALID OpcodeAllowsRepne NaClIllegal
2701 NaClExpVector[0] = {
2702 };
2703 0000000000000000: f2 0f 53 invalid
2704 f2 0f 53 INVALID OpcodeAllowsRepne NaClIllegal
2705 NaClExpVector[0] = {
2706 };
2707 0000000000000000: 66 0f 78 00 00 00 [P] dontcare(ille gal)
2708 66 0f 78 / 0 SSE4A OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed _b OpcodeHasImmed2_b OpcodeAllowsData16 SizeIgnoresData16 NaClIllegal PartialIns truction
2709 DontCare
2710 NaClExpVector[0] = {
2711 };
2712 0000000000000000: 26 e8 00 01 02 03 call 0x3020106
2713 e8 386 OpcodeHasImmed_v OperandSize_v OperandSize_o O perandSizeDefaultIs64 JumpInstruction
2714 Call {%rip}, {%rsp}, $Jzd
2715 RegRIP OpUse OpSet OpImplicit
2716 RegRSP OpUse OpSet OpImplicit
2717 J_Operand OpUse OperandNear OperandRelative
2718 NaClExpVector[6] = {
2719 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
2720 { ExprRegister[0] , %rip, ExprSet | ExprUsed | ExprSize64 },
2721 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
2722 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
2723 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2724 { ExprConstant[0] , 0x3020106, ExprUsed | ExprSize32 | ExprSignedHex | ExprJum pTarget },
2725 };
2726 0000000000000000: 0f a4 c6 01 [P] dontcare %esi (s), %eax (u), 0x1 (u)
2727 0f a4 386 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsD ata16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
2728 DontCare $Ev, $Gv, $Ib
2729 E_Operand OpSet
2730 G_Operand OpUse
2731 I_Operand OpUse
2732 NaClExpVector[6] = {
2733 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2734 { ExprRegister[0] , %esi, ExprSet | ExprSize32 },
2735 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2736 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
2737 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2738 { ExprConstant[0] , 0x1, ExprUsed | ExprSize8 | ExprUnsignedHex },
2739 };
2740 0000000000000000: 0f a5 c6 [P] dontcare %esi (s), %eax (u), %cl (u)
2741 0f a5 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o PartialInstruction
2742 DontCare $Ev, $Gv, %cl
2743 E_Operand OpSet
2744 G_Operand OpUse
2745 RegCL OpUse
2746 NaClExpVector[6] = {
2747 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2748 { ExprRegister[0] , %esi, ExprSet | ExprSize32 },
2749 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2750 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
2751 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2752 { ExprRegister[0] , %cl, ExprUsed | ExprSize8 },
2753 };
2754 0000000000000000: 48 0f a5 c6 [P] dontcare %rsi (s), %rax (u), %cl (u)
2755 0f a5 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o PartialInstruction
2756 DontCare $Ev, $Gv, %cl
2757 E_Operand OpSet
2758 G_Operand OpUse
2759 RegCL OpUse
2760 NaClExpVector[6] = {
2761 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2762 { ExprRegister[0] , %rsi, ExprSet | ExprSize64 },
2763 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2764 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2765 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2766 { ExprRegister[0] , %cl, ExprUsed | ExprSize8 },
2767 };
2768 0000000000000000: 0f 16 d1 [P] dontcare %xmm 1 (u)
2769 0f 16 SSE ModRmModIs0x3 OpcodeUsesModRm PartialInstructi on
2770 DontCare $VRq
2771 Xmm_E_Operand OpUse
2772 NaClExpVector[2] = {
2773 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2774 { ExprRegister[0] , %xmm1, ExprUsed },
2775 };
2776 0000000000000000: 0f 16 a5 00 00 00 00 [P] dontcare [%rb p] (u)
2777 0f 16 SSE ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruc tion
2778 DontCare $Mq
2779 Mo_Operand OpUse
2780 NaClExpVector[6] = {
2781 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2782 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2783 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
2784 { ExprRegister[0] , %unknown, 0 },
2785 { ExprConstant[0] , 1, ExprSize8 },
2786 { ExprConstant[0] , 0x0, ExprSize32 | ExprSignedHex },
2787 };
2788 0000000000000000: 0f 12 e8 [P] dontcare %xmm 0 (u)
2789 0f 12 SSE ModRmModIs0x3 OpcodeUsesModRm PartialInstructi on
2790 DontCare $VRq
2791 Xmm_E_Operand OpUse
2792 NaClExpVector[2] = {
2793 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2794 { ExprRegister[0] , %xmm0, ExprUsed },
2795 };
2796 0000000000000000: 0f 12 0c 17 [P] dontcare [%rd i+%rdx*1] (u)
2797 0f 12 SSE ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruc tion
2798 DontCare $Mq
2799 Mo_Operand OpUse
2800 NaClExpVector[6] = {
2801 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2802 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2803 { ExprRegister[0] , %rdi, ExprUsed | ExprSize64 },
2804 { ExprRegister[0] , %rdx, ExprUsed | ExprSize64 },
2805 { ExprConstant[0] , 1, ExprSize8 },
2806 { ExprConstant[0] , 0, ExprSize8 },
2807 };
2808 0000000000000000: 41 0f 12 0c 17 [P] dontcare [%r1 5+%rdx*1] (u)
2809 0f 12 SSE ModRmModIsnt0x3 OpcodeUsesModRm PartialInstruc tion
2810 DontCare $Mq
2811 Mo_Operand OpUse
2812 NaClExpVector[6] = {
2813 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2814 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2815 { ExprRegister[0] , %r15, ExprUsed | ExprSize64 },
2816 { ExprRegister[0] , %rdx, ExprUsed | ExprSize64 },
2817 { ExprConstant[0] , 1, ExprSize8 },
2818 { ExprConstant[0] , 0, ExprSize8 },
2819 };
2820 0000000000000000: 0f c6 d2 00 [P] dontcare %xmm 2 (u), 0x0 (u)
2821 0f c6 SSE OpcodeUsesModRm OpcodeHasImmed_b PartialInstru ction
2822 DontCare $Wps, $Ib
2823 Xmm_E_Operand OpUse
2824 I_Operand OpUse
2825 NaClExpVector[4] = {
2826 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2827 { ExprRegister[0] , %xmm2, ExprUsed },
2828 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2829 { ExprConstant[0] , 0x0, ExprUsed | ExprSize8 | ExprUnsignedHex },
2830 };
2831 0000000000000000: 66 0f c6 d2 00 [P] dontcare %xmm 2 (u), 0x0 (u)
2832 66 0f c6 SSE2 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllows Data16 SizeIgnoresData16 PartialInstruction
2833 DontCare $Wpd, $Ib
2834 Xmm_E_Operand OpUse
2835 I_Operand OpUse
2836 NaClExpVector[4] = {
2837 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2838 { ExprRegister[0] , %xmm2, ExprUsed },
2839 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2840 { ExprConstant[0] , 0x0, ExprUsed | ExprSize8 | ExprUnsignedHex },
2841 };
2842 0000000000000000: 66 43 0f be 04 27 [P] dontcare %ax (sz), [%r15+%r12*1] (u)
2843 0f be 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o PartialInstruction
2844 DontCare $Gv, $Eb
2845 G_Operand OpSet OperandZeroExtends_v
2846 Eb_Operand OpUse
2847 NaClExpVector[8] = {
2848 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2849 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
2850 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2851 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2852 { ExprRegister[0] , %r15, ExprUsed | ExprSize64 },
2853 { ExprRegister[0] , %r12, ExprUsed | ExprSize64 },
2854 { ExprConstant[0] , 1, ExprSize8 },
2855 { ExprConstant[0] , 0, ExprSize8 },
2856 };
2857 0000000000000000: 0f 30 [P] dontcare(ille gal)
2858 0f 30 RDMSR NaClIllegal PartialInstruction
2859 DontCare
2860 NaClExpVector[0] = {
2861 };
2862 0000000000000000: 0f 31 [P] dontcare %eax (s), %edx (s)
2863 0f 31 RDTSC PartialInstruction
2864 DontCare %eax, %edx
2865 RegEAX OpSet
2866 RegEDX OpSet
2867 NaClExpVector[4] = {
2868 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2869 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
2870 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2871 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
2872 };
2873 0000000000000000: 0f 32 [P] dontcare(ille gal)
2874 0f 32 RDMSR NaClIllegal PartialInstruction
2875 DontCare
2876 NaClExpVector[0] = {
2877 };
2878 0000000000000000: 48 0f ac c1 10 [P] dontcare %rcx (su), %rax (u), 0x10 (u)
2879 0f ac 386 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsD ata16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
2880 DontCare $Ev, $Gv, $Ib
2881 E_Operand OpUse OpSet
2882 G_Operand OpUse
2883 I_Operand OpUse
2884 NaClExpVector[6] = {
2885 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2886 { ExprRegister[0] , %rcx, ExprSet | ExprUsed | ExprSize64 },
2887 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2888 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2889 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2890 { ExprConstant[0] , 0x10, ExprUsed | ExprSize8 | ExprUnsignedHex },
2891 };
2892 0000000000000000: 0f ac c1 10 [P] dontcare %ecx (su), %eax (u), 0x10 (u)
2893 0f ac 386 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsD ata16 OperandSize_w OperandSize_v OperandSize_o PartialInstruction
2894 DontCare $Ev, $Gv, $Ib
2895 E_Operand OpUse OpSet
2896 G_Operand OpUse
2897 I_Operand OpUse
2898 NaClExpVector[6] = {
2899 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2900 { ExprRegister[0] , %ecx, ExprSet | ExprUsed | ExprSize32 },
2901 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2902 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
2903 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2904 { ExprConstant[0] , 0x10, ExprUsed | ExprSize8 | ExprUnsignedHex },
2905 };
2906 0000000000000000: 0f ad 45 bc [P] dontcare [%rb p-0x44] (su), %eax (u), %cl (u)
2907 0f ad 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o PartialInstruction
2908 DontCare $Ev, $Gv, %cl
2909 E_Operand OpUse OpSet
2910 G_Operand OpUse
2911 RegCL OpUse
2912 NaClExpVector[10] = {
2913 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2914 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2915 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
2916 { ExprRegister[0] , %unknown, 0 },
2917 { ExprConstant[0] , 1, ExprSize8 },
2918 { ExprConstant[0] , -0x44, ExprSize8 | ExprSignedHex },
2919 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2920 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
2921 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2922 { ExprRegister[0] , %cl, ExprUsed | ExprSize8 },
2923 };
2924 0000000000000000: 48 0f ad 45 bc [P] dontcare [%rb p-0x44] (su), %rax (u), %cl (u)
2925 0f ad 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o PartialInstruction
2926 DontCare $Ev, $Gv, %cl
2927 E_Operand OpUse OpSet
2928 G_Operand OpUse
2929 RegCL OpUse
2930 NaClExpVector[10] = {
2931 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2932 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2933 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
2934 { ExprRegister[0] , %unknown, 0 },
2935 { ExprConstant[0] , 1, ExprSize8 },
2936 { ExprConstant[0] , -0x44, ExprSize8 | ExprSignedHex },
2937 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2938 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2939 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2940 { ExprRegister[0] , %cl, ExprUsed | ExprSize8 },
2941 };
2942 0000000000000000: 8c 00 [P] dontcare(ille gal)
2943 8c 386 ModRmRegSOperand OpcodeUsesModRm OpcodeAllowsD ata16 OperandSize_w OperandSize_v OperandSize_o NaClIllegal PartialInstruction
2944 DontCare
2945 NaClExpVector[0] = {
2946 };
2947 0000000000000000: 64 48 8e 00 [P] dontcare(ille gal)
2948 8e 386 ModRmRegSOperand OpcodeUsesModRm NaClIllegal P artialInstruction
2949 DontCare
2950 NaClExpVector[0] = {
2951 };
2952 0000000000000000: 26 64 65 00 01 add %gs:[%rcx], % al
2953 00 386 OpcodeUsesModRm OpcodeLockable OperandSize_b
2954 Add $Eb, $Gb
2955 E_Operand OpUse OpSet
2956 G_Operand OpUse
2957 NaClExpVector[10] = {
2958 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2959 { ExprSegmentAddress[2] , 0, ExprSet | ExprUsed | ExprSize64 },
2960 { ExprRegister[0] , %gs, ExprUsed | ExprSize16 },
2961 { ExprMemOffset[4] , 0, ExprSize64 },
2962 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
2963 { ExprRegister[0] , %unknown, 0 },
2964 { ExprConstant[0] , 1, ExprSize8 },
2965 { ExprConstant[0] , 0, ExprSize8 },
2966 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2967 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
2968 };
2969 0000000000000000: 0f a3 00 [P] dontcare(ille gal)
2970 0f a3 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o NaClIllegal PartialInstruction
2971 DontCare
2972 NaClExpVector[0] = {
2973 };
2974 0000000000000000: 0f a3 04 00 [P] dontcare(ille gal)
2975 0f a3 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o NaClIllegal PartialInstruction
2976 DontCare
2977 NaClExpVector[0] = {
2978 };
2979 0000000000000000: 0f a3 80 00 01 02 03 [P] dontcare(ille gal)
2980 0f a3 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o NaClIllegal PartialInstruction
2981 DontCare
2982 NaClExpVector[0] = {
2983 };
2984 0000000000000000: 36 64 6f [P] dontcare(ille gal)
2985 6f 386 OpcodeAllowsRep OperandSize_v OperandSize_o Na ClIllegal PartialInstruction
2986 DontCare
2987 NaClExpVector[0] = {
2988 };
2989 0000000000000000: 64 40 a0 00 01 02 03 04 05 06 07 mov %al, %fs:[0x7 06050403020100]
2990 a0 386 OpcodeHasImmed_Addr OperandSize_b
2991 Mov %al, $Ob
2992 RegAL OpSet
2993 O_Operand OpUse
2994 NaClExpVector[10] = {
2995 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2996 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
2997 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2998 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 },
2999 { ExprRegister[0] , %fs, ExprUsed | ExprSize16 },
3000 { ExprMemOffset[4] , 0, ExprSize64 },
3001 { ExprRegister[0] , %unknown, 0 },
3002 { ExprRegister[0] , %unknown, 0 },
3003 { ExprConstant[0] , 1, ExprSize8 },
3004 { ExprConstant[0] , 0x706050403020100, ExprSize64 | ExprUnsignedHex },
3005 };
3006 0000000000000000: 0f 01 c8 [P] dontcare(ille gal)
3007 0f 01 / 1 / 0 SYSTEM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 OpcodeUsesModRm NaClIllegal PartialInstruction
3008 DontCare
3009 NaClExpVector[0] = {
3010 };
3011 0000000000000000: 0f 01 c9 [P] dontcare(ille gal)
3012 0f 01 / 1 / 1 SYSTEM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 OpcodeUsesModRm NaClIllegal PartialInstruction
3013 DontCare
3014 NaClExpVector[0] = {
3015 };
3016 0000000000000000: 0f 01 f8 [P] dontcare(ille gal)
3017 0f 01 / 7 / 0 SYSTEM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 OpcodeUsesModRm NaClIllegal LongMode PartialInstruction
3018 DontCare
3019 NaClExpVector[0] = {
3020 };
3021 0000000000000000: 0f 01 f9 [P] dontcare(ille gal)
3022 0f 01 / 7 / 1 RDTSCP OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 OpcodeUsesModRm NaClIllegal PartialInstruction
3023 DontCare
3024 NaClExpVector[0] = {
3025 };
3026 0000000000000000: 0f 01 d8 [P] dontcare(ille gal)
3027 0f 01 / 3 / 0 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal PartialInstruction
3028 DontCare
3029 NaClExpVector[0] = {
3030 };
3031 0000000000000000: 0f 01 d9 [P] dontcare(ille gal)
3032 0f 01 / 3 / 1 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal PartialInstruction
3033 DontCare
3034 NaClExpVector[0] = {
3035 };
3036 0000000000000000: 0f 01 da [P] dontcare(ille gal)
3037 0f 01 / 3 / 2 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal PartialInstruction
3038 DontCare
3039 NaClExpVector[0] = {
3040 };
3041 0000000000000000: 0f 01 db [P] dontcare(ille gal)
3042 0f 01 / 3 / 3 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal PartialInstruction
3043 DontCare
3044 NaClExpVector[0] = {
3045 };
3046 0000000000000000: 0f 01 dc [P] dontcare(ille gal)
3047 0f 01 / 3 / 4 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal PartialInstruction
3048 DontCare
3049 NaClExpVector[0] = {
3050 };
3051 0000000000000000: 0f 01 dd [P] dontcare(ille gal)
3052 0f 01 / 3 / 5 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal PartialInstruction
3053 DontCare
3054 NaClExpVector[0] = {
3055 };
3056 0000000000000000: 0f 01 de [P] dontcare(ille gal)
3057 0f 01 / 3 / 6 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal PartialInstruction
3058 DontCare
3059 NaClExpVector[0] = {
3060 };
3061 0000000000000000: 0f 01 df [P] dontcare(ille gal)
3062 0f 01 / 3 / 7 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal PartialInstruction
3063 DontCare
3064 NaClExpVector[0] = {
3065 };
3066 0000000000000000: 0f 20 c0 [P] dontcare(ille gal)
3067 0f 20 SYSTEM ModRmModIs0x3 OpcodeUsesModRm NaClIllegal P artialInstruction
3068 DontCare
3069 NaClExpVector[0] = {
3070 };
3071 0000000000000000: 0f 21 f3 [P] dontcare(ille gal)
3072 0f 21 SYSTEM ModRmModIs0x3 OpcodeUsesModRm NaClIllegal P artialInstruction
3073 DontCare
3074 NaClExpVector[0] = {
3075 };
3076 0000000000000000: 0f 22 cd [P] dontcare(ille gal)
3077 0f 22 SYSTEM ModRmModIs0x3 OpcodeUsesModRm NaClIllegal P artialInstruction
3078 DontCare
3079 NaClExpVector[0] = {
3080 };
3081 0000000000000000: 0f 23 dd [P] dontcare(ille gal)
3082 0f 23 SYSTEM ModRmModIs0x3 OpcodeUsesModRm NaClIllegal P artialInstruction
3083 DontCare
3084 NaClExpVector[0] = {
3085 };
3086 0000000000000000: 0f 0f 00 00 invalid %mmx0, [% rax], 0x0
3087 0f 0f INVALID Opcode0F0F OpcodeUsesModRm OpcodeHasImmed_ b NaClIllegal
3088 Invalid $Pq, $Qq, $Ib
3089 Mmx_G_Operand
3090 Mmx_E_Operand
3091 I_Operand
3092 NaClExpVector[10] = {
3093 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3094 { ExprRegister[0] , %mmx0, 0 },
3095 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3096 { ExprMemOffset[4] , 0, ExprSize64 },
3097 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3098 { ExprRegister[0] , %unknown, 0 },
3099 { ExprConstant[0] , 1, ExprSize8 },
3100 { ExprConstant[0] , 0, ExprSize8 },
3101 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3102 { ExprConstant[0] , 0x0, ExprSize8 | ExprUnsignedHex },
3103 };
3104 0000000000000000: 0f 0f 00 90 [P] dontcare [%ra x] (u)
3105 0f 0f 90 3DNOW OpcodeUsesModRm PartialInstruction
3106 DontCare $Qq
3107 Mmx_E_Operand OpUse
3108 NaClExpVector[6] = {
3109 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3110 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
3111 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3112 { ExprRegister[0] , %unknown, 0 },
3113 { ExprConstant[0] , 1, ExprSize8 },
3114 { ExprConstant[0] , 0, ExprSize8 },
3115 };
3116 0000000000000000: 8d bf 00 00 00 00 lea %edi, [%rdi]
3117 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
3118 Lea $Gv, $M
3119 G_Operand OpSet OperandZeroExtends_v
3120 M_Operand OpAddress
3121 NaClExpVector[8] = {
3122 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3123 { ExprRegister[0] , %edi, ExprSet | ExprSize32 },
3124 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3125 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
3126 { ExprRegister[0] , %rdi, ExprUsed | ExprSize64 },
3127 { ExprRegister[0] , %unknown, 0 },
3128 { ExprConstant[0] , 1, ExprSize8 },
3129 { ExprConstant[0] , 0x0, ExprSize32 | ExprSignedHex },
3130 };
3131 0000000000000000: eb 1d [P] dontcarejump %rip (s), 0x1f (u)
3132 eb 386 OpcodeHasImmed OperandSize_b JumpInstruction P artialInstruction
3133 DontCareJump %rip, $Jb
3134 RegRIP OpSet
3135 J_Operand OpUse OperandNear OperandRelative
3136 NaClExpVector[4] = {
3137 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3138 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
3139 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3140 { ExprConstant[0] , 0x1f, ExprUsed | ExprSize8 | ExprSignedHex | ExprJumpTarge t },
3141 };
3142 0000000000000000: f0 0f c7 08 [P] dontcare %edx (su), %eax (su), [%rax] (su)
3143 0f c7 / 1 CMPXCHG8B OpcodeInModRm ModRmModIsnt0x3 OpcodeUses ModRm OpcodeLockable OperandSize_v PartialInstruction
3144 DontCare %edx, %eax, $Mq
3145 RegEDX OpUse OpSet
3146 RegEAX OpUse OpSet
3147 Mo_Operand OpUse OpSet
3148 NaClExpVector[10] = {
3149 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3150 { ExprRegister[0] , %edx, ExprSet | ExprUsed | ExprSize32 },
3151 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3152 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
3153 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3154 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
3155 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3156 { ExprRegister[0] , %unknown, 0 },
3157 { ExprConstant[0] , 1, ExprSize8 },
3158 { ExprConstant[0] , 0, ExprSize8 },
3159 };
3160 0000000000000000: 48 f0 0f c7 08 [P] dontcare %rdx (su), %eax (su), [%rax] (su)
3161 0f c7 / 1 CMPXCHG16B OpcodeInModRm ModRmModIsnt0x3 OpcodeUse sModRm OpcodeLockable OperandSize_o PartialInstruction
3162 DontCare %rdx, %eax, $Mdq
3163 RegRDX OpUse OpSet
3164 RegEAX OpUse OpSet
3165 Mdq_Operand OpUse OpSet
3166 NaClExpVector[10] = {
3167 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3168 { ExprRegister[0] , %rdx, ExprSet | ExprUsed | ExprSize64 },
3169 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3170 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
3171 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3172 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
3173 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3174 { ExprRegister[0] , %unknown, 0 },
3175 { ExprConstant[0] , 1, ExprSize8 },
3176 { ExprConstant[0] , 0, ExprSize8 },
3177 };
3178 0000000000000000: f0 48 0f c7 08 [P] dontcare %rdx (su), %eax (su), [%rax] (su)
3179 0f c7 / 1 CMPXCHG16B OpcodeInModRm ModRmModIsnt0x3 OpcodeUse sModRm OpcodeLockable OperandSize_o PartialInstruction
3180 DontCare %rdx, %eax, $Mdq
3181 RegRDX OpUse OpSet
3182 RegEAX OpUse OpSet
3183 Mdq_Operand OpUse OpSet
3184 NaClExpVector[10] = {
3185 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3186 { ExprRegister[0] , %rdx, ExprSet | ExprUsed | ExprSize64 },
3187 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3188 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
3189 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3190 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
3191 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3192 { ExprRegister[0] , %unknown, 0 },
3193 { ExprConstant[0] , 1, ExprSize8 },
3194 { ExprConstant[0] , 0, ExprSize8 },
3195 };
3196 0000000000000000: 66 48 0f 7e c6 [P] dontcare %rsi (s)
3197 66 0f 7e SSE2 OpcodeUsesModRm OpcodeAllowsData16 SizeIgnore sData16 OperandSize_o PartialInstruction
3198 DontCare $Ed/q/q
3199 E_Operand OpSet
3200 NaClExpVector[2] = {
3201 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3202 { ExprRegister[0] , %rsi, ExprSet | ExprSize64 },
3203 };
3204 0000000000000000: 48 0f 7e c6 [P] dontcare %rsi (s)
3205 0f 7e MMX OpcodeUsesModRm SizeIgnoresData16 OperandSize_ o PartialInstruction
3206 DontCare $Ed/q/q
3207 E_Operand OpSet
3208 NaClExpVector[2] = {
3209 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3210 { ExprRegister[0] , %rsi, ExprSet | ExprSize64 },
3211 };
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