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Issue 625923004: Delete old x86 validator. (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client
Patch Set: rebase master Created 6 years, 2 months ago
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1 0000000000000000: 00 c0 add %al, %al
2 00 386 OpcodeUsesModRm OpcodeLockable OperandSize_b
3 Add $Eb, $Gb
4 E_Operand OpUse OpSet
5 G_Operand OpUse
6 NaClExpVector[4] = {
7 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
8 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
9 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
10 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
11 };
12 0000000000000000: 01 c0 add %eax, %eax
13 01 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
14 Add $Ev, $Gv
15 E_Operand OpUse OpSet OperandZeroExtends_v
16 G_Operand OpUse
17 NaClExpVector[4] = {
18 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
19 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
20 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
21 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
22 };
23 0000000000000000: 41 01 c3 add %r11d, %eax
24 01 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
25 Add $Ev, $Gv
26 E_Operand OpUse OpSet OperandZeroExtends_v
27 G_Operand OpUse
28 NaClExpVector[4] = {
29 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
30 { ExprRegister[0] , %r11d, ExprSet | ExprUsed | ExprSize32 },
31 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
32 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
33 };
34 0000000000000000: 44 01 d8 add %eax, %r11d
35 01 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
36 Add $Ev, $Gv
37 E_Operand OpUse OpSet OperandZeroExtends_v
38 G_Operand OpUse
39 NaClExpVector[4] = {
40 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
41 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
42 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
43 { ExprRegister[0] , %r11d, ExprUsed | ExprSize32 },
44 };
45 0000000000000000: 48 01 c3 add %rbx, %rax
46 01 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
47 Add $Ev, $Gv
48 E_Operand OpUse OpSet OperandZeroExtends_v
49 G_Operand OpUse
50 NaClExpVector[4] = {
51 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
52 { ExprRegister[0] , %rbx, ExprSet | ExprUsed | ExprSize64 },
53 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
54 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
55 };
56 0000000000000000: 67 03 18 add %ebx, [%eax]
57 03 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
58 Add $Gv, $Ev
59 G_Operand OpUse OpSet OperandZeroExtends_v
60 E_Operand OpUse
61 NaClExpVector[8] = {
62 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
63 { ExprRegister[0] , %ebx, ExprSet | ExprUsed | ExprSize32 },
64 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
65 { ExprMemOffset[4] , 0, ExprUsed | ExprSize32 },
66 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
67 { ExprRegister[0] , %unknown, 0 },
68 { ExprConstant[0] , 1, ExprSize8 },
69 { ExprConstant[0] , 0, ExprSize8 },
70 };
71 0000000000000000: 02 04 00 add %al, [%rax+%r ax*1]
72 02 386 OpcodeUsesModRm OpcodeLockable OperandSize_b
73 Add $Gb, $Eb
74 G_Operand OpUse OpSet
75 E_Operand OpUse
76 NaClExpVector[8] = {
77 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
78 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
79 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
80 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
81 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
82 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
83 { ExprConstant[0] , 1, ExprSize8 },
84 { ExprConstant[0] , 0, ExprSize8 },
85 };
86 0000000000000000: 67 02 04 00 add %al, [%eax+%e ax*1]
87 02 386 OpcodeUsesModRm OpcodeLockable OperandSize_b
88 Add $Gb, $Eb
89 G_Operand OpUse OpSet
90 E_Operand OpUse
91 NaClExpVector[8] = {
92 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
93 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
94 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
95 { ExprMemOffset[4] , 0, ExprUsed | ExprSize32 },
96 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
97 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
98 { ExprConstant[0] , 1, ExprSize8 },
99 { ExprConstant[0] , 0, ExprSize8 },
100 };
101 0000000000000000: 48 83 ec 08 sub %rsp, 0x8
102 83 / 5 386 OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed_b OpcodeLockable OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
103 Sub $Ev, $Ib
104 E_Operand OpUse OpSet OperandZeroExtends_v
105 I_Operand OpUse
106 NaClExpVector[4] = {
107 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
108 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
109 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
110 { ExprConstant[0] , 0x8, ExprUsed | ExprSize8 | ExprUnsignedHex },
111 };
112 00000000004003d4: e8 83 00 00 00 call 0x40045c
113 e8 386 OpcodeHasImmed_v OperandSize_v OperandSize_o O perandSizeDefaultIs64 JumpInstruction
114 Call {%rip}, {%rsp}, $Jzd
115 RegRIP OpUse OpSet OpImplicit
116 RegRSP OpUse OpSet OpImplicit
117 J_Operand OpUse OperandNear OperandRelative
118 NaClExpVector[6] = {
119 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
120 { ExprRegister[0] , %rip, ExprSet | ExprUsed | ExprSize64 },
121 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
122 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
123 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
124 { ExprConstant[0] , 0x40045c, ExprUsed | ExprSize32 | ExprSignedHex | ExprJump Target },
125 };
126 00000000004003de: e8 7d 05 00 00 call 0x400960
127 e8 386 OpcodeHasImmed_v OperandSize_v OperandSize_o O perandSizeDefaultIs64 JumpInstruction
128 Call {%rip}, {%rsp}, $Jzd
129 RegRIP OpUse OpSet OpImplicit
130 RegRSP OpUse OpSet OpImplicit
131 J_Operand OpUse OperandNear OperandRelative
132 NaClExpVector[6] = {
133 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
134 { ExprRegister[0] , %rip, ExprSet | ExprUsed | ExprSize64 },
135 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
136 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
137 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
138 { ExprConstant[0] , 0x400960, ExprUsed | ExprSize32 | ExprSignedHex | ExprJump Target },
139 };
140 0000000000000000: c3 ret
141 c3 386 NaClIllegal OperandSizeDefaultIs64
142 Ret {%rip}, {%rsp}
143 RegRIP OpSet OpImplicit
144 RegRSP OpUse OpSet OpImplicit
145 NaClExpVector[4] = {
146 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
147 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
148 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
149 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
150 };
151 0000000000000000: ff 35 ea 0d 20 00 push [%rip+0x200d ea]
152 ff / 6 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o OperandSizeDefaultIs64
153 Push {%rsp}, $Ev
154 RegRSP OpUse OpSet OpImplicit
155 E_Operand OpUse
156 NaClExpVector[8] = {
157 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
158 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
159 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
160 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
161 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
162 { ExprRegister[0] , %unknown, 0 },
163 { ExprConstant[0] , 1, ExprSize8 },
164 { ExprConstant[0] , 0x200dea, ExprSize32 | ExprSignedHex },
165 };
166 0000000000000000: ff 25 ec 0d 20 00 jmp [%rip+0x200de c]
167 ff / 4 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o OperandSizeDefaultIs64 JumpInstruct ion
168 Jmp {%rip}, $Ev
169 RegRIP OpSet OpImplicit
170 E_Operand OpUse OperandNear
171 NaClExpVector[8] = {
172 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
173 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
174 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
175 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 | ExprJumpTarget },
176 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
177 { ExprRegister[0] , %unknown, 0 },
178 { ExprConstant[0] , 1, ExprSize8 },
179 { ExprConstant[0] , 0x200dec, ExprSize32 | ExprSignedHex },
180 };
181 0000000000000000: 0f 1f 40 00 nop
182 [hard coded] 386
183 Nop
184 NaClExpVector[0] = {
185 };
186 0000000000000000: 68 00 00 00 00 push 0x0
187 68 386 OpcodeHasImmed_z OpcodeAllowsData16 OperandSiz eDefaultIs64
188 Push {%rsp}, $Iz
189 RegRSP OpUse OpSet OpImplicit
190 I_Operand OpUse
191 NaClExpVector[4] = {
192 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
193 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
194 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
195 { ExprConstant[0] , 0x0, ExprUsed | ExprSize32 | ExprUnsignedHex },
196 };
197 0000000000400403: e9 e0 ff ff ff jmp 0x4003e8
198 e9 386 OpcodeHasImmed_v OperandSize_v OperandSize_o O perandSizeDefaultIs64 JumpInstruction
199 Jmp {%rip}, $Jzd
200 RegRIP OpSet OpImplicit
201 J_Operand OpUse OperandNear OperandRelative
202 NaClExpVector[4] = {
203 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
204 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
205 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
206 { ExprConstant[0] , 0x4003e8, ExprUsed | ExprSize32 | ExprSignedHex | ExprJump Target },
207 };
208 0000000000000000: 49 89 d1 mov %r9, %rdx
209 89 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
210 Mov $Ev, $Gv
211 E_Operand OpSet OperandZeroExtends_v
212 G_Operand OpUse
213 NaClExpVector[4] = {
214 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
215 { ExprRegister[0] , %r9, ExprSet | ExprSize64 },
216 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
217 { ExprRegister[0] , %rdx, ExprUsed | ExprSize64 },
218 };
219 0000000000000000: 5e pop %rsi
220 5e - r6 386 OpcodePlusR OpcodeAllowsData16 OperandSize_w O perandSize_v OperandSize_o OperandSizeDefaultIs64
221 Pop {%rsp}, $r8v
222 RegRSP OpUse OpSet OpImplicit
223 G_OpcodeBase OpSet
224 NaClExpVector[4] = {
225 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
226 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
227 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
228 { ExprRegister[0] , %rsi, ExprSet | ExprSize64 },
229 };
230 0000000000000000: 49 c7 c0 c0 08 40 00 mov %r8, 0x4008c0
231 c7 / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed_z OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
232 Mov $Ev, $Iz
233 E_Operand OpSet OperandZeroExtends_v
234 I_Operand OpUse
235 NaClExpVector[4] = {
236 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
237 { ExprRegister[0] , %r8, ExprSet | ExprSize64 },
238 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
239 { ExprConstant[0] , 0x4008c0, ExprUsed | ExprSize32 | ExprUnsignedHex },
240 };
241 0000000000000000: f4 hlt
242 f4 386
243 Hlt
244 NaClExpVector[0] = {
245 };
246 0000000000000000: 48 8b 05 61 0d 20 00 mov %rax, [%rip+0 x200d61]
247 8b 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
248 Mov $Gv, $Ev
249 G_Operand OpSet OperandZeroExtends_v
250 E_Operand OpUse
251 NaClExpVector[8] = {
252 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
253 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
254 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
255 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
256 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
257 { ExprRegister[0] , %unknown, 0 },
258 { ExprConstant[0] , 1, ExprSize8 },
259 { ExprConstant[0] , 0x200d61, ExprSize32 | ExprSignedHex },
260 };
261 0000000000000000: 48 85 c0 test %rax, %rax
262 85 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
263 Test $Ev, $Gv
264 E_Operand OpUse
265 G_Operand OpUse
266 NaClExpVector[4] = {
267 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
268 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
269 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
270 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
271 };
272 000000000040046a: 74 02 jz 0x40046e
273 74 386 OpcodeHasImmed OperandSize_b ConditionalJump B ranchHints
274 Jz {%rip}, $Jb
275 RegRIP OpSet OpImplicit
276 J_Operand OpUse OperandNear OperandRelative
277 NaClExpVector[4] = {
278 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
279 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
280 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
281 { ExprConstant[0] , 0x40046e, ExprUsed | ExprSize8 | ExprSignedHex | ExprJumpT arget },
282 };
283 0000000000000000: ff d0 call %rax
284 ff / 2 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o OperandSizeDefaultIs64 JumpInstruct ion
285 Call {%rip}, {%rsp}, $Ev
286 RegRIP OpUse OpSet OpImplicit
287 RegRSP OpUse OpSet OpImplicit
288 E_Operand OpUse OperandNear
289 NaClExpVector[6] = {
290 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
291 { ExprRegister[0] , %rip, ExprSet | ExprUsed | ExprSize64 },
292 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
293 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
294 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
295 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 | ExprJumpTarget },
296 };
297 000000000040048d: eb 24 jmp 0x4004b3
298 eb 386 OpcodeHasImmed OperandSize_b JumpInstruction
299 Jmp {%rip}, $Jb
300 RegRIP OpSet OpImplicit
301 J_Operand OpUse OperandNear OperandRelative
302 NaClExpVector[4] = {
303 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
304 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
305 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
306 { ExprConstant[0] , 0x4004b3, ExprUsed | ExprSize8 | ExprSignedHex | ExprJumpT arget },
307 };
308 0000000000000000: c9 leave
309 c9 386 NaClIllegal OperandSizeDefaultIs64
310 Leave {%rsp}, {%rbp}
311 RegRSP OpSet OpImplicit
312 RegRBP OpUse OpSet OpImplicit
313 NaClExpVector[4] = {
314 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
315 { ExprRegister[0] , %rsp, ExprSet | ExprSize64 },
316 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
317 { ExprRegister[0] , %rbp, ExprSet | ExprUsed | ExprSize64 },
318 };
319 0000000000000000: 66 66 2e 0f 1f 84 00 00 00 00 00 nop
320 [hard coded] 386
321 Nop
322 NaClExpVector[0] = {
323 };
324 0000000000000000: b8 00 00 00 00 mov %eax, 0x0
325 b8 - r0 386 OpcodeHasImmed OpcodePlusR OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
326 Mov $r8v, $Iv
327 G_OpcodeBase OpSet OperandZeroExtends_v
328 I_Operand OpUse
329 NaClExpVector[4] = {
330 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
331 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
332 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
333 { ExprConstant[0] , 0x0, ExprUsed | ExprSize32 | ExprUnsignedHex },
334 };
335 0000000000000000: bf 20 10 60 00 mov %edi, 0x60102 0
336 bf - r7 386 OpcodeHasImmed OpcodePlusR OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
337 Mov $r8v, $Iv
338 G_OpcodeBase OpSet OperandZeroExtends_v
339 I_Operand OpUse
340 NaClExpVector[4] = {
341 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
342 { ExprRegister[0] , %edi, ExprSet | ExprSize32 },
343 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
344 { ExprConstant[0] , 0x601020, ExprUsed | ExprSize32 | ExprUnsignedHex },
345 };
346 0000000000000000: 48 8b 04 c5 a0 13 60 00 mov %rax, [%rax*8 +0x6013a0]
347 8b 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
348 Mov $Gv, $Ev
349 G_Operand OpSet OperandZeroExtends_v
350 E_Operand OpUse
351 NaClExpVector[8] = {
352 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
353 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
354 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
355 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
356 { ExprRegister[0] , %unknown, 0 },
357 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
358 { ExprConstant[0] , 8, ExprSize8 },
359 { ExprConstant[0] , 0x6013a0, ExprSize32 | ExprSignedHex },
360 };
361 0000000000000000: 89 7d fc mov [%rbp-0x4], % edi
362 89 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
363 Mov $Ev, $Gv
364 E_Operand OpSet OperandZeroExtends_v
365 G_Operand OpUse
366 NaClExpVector[8] = {
367 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
368 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
369 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
370 { ExprRegister[0] , %unknown, 0 },
371 { ExprConstant[0] , 1, ExprSize8 },
372 { ExprConstant[0] , -0x4, ExprSize8 | ExprSignedHex },
373 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
374 { ExprRegister[0] , %edi, ExprUsed | ExprSize32 },
375 };
376 0000000000000000: 3b 45 fc cmp %eax, [%rbp-0 x4]
377 3b 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
378 Cmp $Gv, $Ev
379 G_Operand OpUse
380 E_Operand OpUse
381 NaClExpVector[8] = {
382 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
383 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
384 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
385 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
386 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
387 { ExprRegister[0] , %unknown, 0 },
388 { ExprConstant[0] , 1, ExprSize8 },
389 { ExprConstant[0] , -0x4, ExprSize8 | ExprSignedHex },
390 };
391 0000000000000000: 83 7d f8 08 cmp [%rbp-0x8], 0 x8
392 83 / 7 386 OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
393 Cmp $Ev, $Ib
394 E_Operand OpUse
395 I_Operand OpUse
396 NaClExpVector[8] = {
397 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
398 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
399 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
400 { ExprRegister[0] , %unknown, 0 },
401 { ExprConstant[0] , 1, ExprSize8 },
402 { ExprConstant[0] , -0x8, ExprSize8 | ExprSignedHex },
403 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
404 { ExprConstant[0] , 0x8, ExprUsed | ExprSize8 | ExprUnsignedHex },
405 };
406 0000000000000000: 8b 45 fc mov %eax, [%rbp-0 x4]
407 8b 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
408 Mov $Gv, $Ev
409 G_Operand OpSet OperandZeroExtends_v
410 E_Operand OpUse
411 NaClExpVector[8] = {
412 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
413 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
414 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
415 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
416 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
417 { ExprRegister[0] , %unknown, 0 },
418 { ExprConstant[0] , 1, ExprSize8 },
419 { ExprConstant[0] , -0x4, ExprSize8 | ExprSignedHex },
420 };
421 0000000000000000: 41 d3 e4 shl %r12d, %cl
422 d3 / 4 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o
423 Shl $Ev, %cl
424 E_Operand OpUse OpSet
425 RegCL OpUse
426 NaClExpVector[4] = {
427 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
428 { ExprRegister[0] , %r12d, ExprSet | ExprUsed | ExprSize32 },
429 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
430 { ExprRegister[0] , %cl, ExprUsed | ExprSize8 },
431 };
432 0000000000000000: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nop
433 [hard coded] 386
434 Nop
435 NaClExpVector[0] = {
436 };
437 0000000000000000: 48 c1 fd 03 sar %rbp, 0x3
438 c1 / 7 386 OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
439 Sar $Ev, $Ib
440 E_Operand OpUse OpSet
441 I_Operand OpUse
442 NaClExpVector[4] = {
443 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
444 { ExprRegister[0] , %rbp, ExprSet | ExprUsed | ExprSize64 },
445 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
446 { ExprConstant[0] , 0x3, ExprUsed | ExprSize8 | ExprUnsignedHex },
447 };
448 0000000000000000: 48 8d 2d 0f 07 20 00 lea %rbp, [%rip+0 x20070f]
449 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
450 Lea $Gv, $M
451 G_Operand OpSet OperandZeroExtends_v
452 M_Operand OpAddress
453 NaClExpVector[8] = {
454 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
455 { ExprRegister[0] , %rbp, ExprSet | ExprSize64 },
456 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
457 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
458 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
459 { ExprRegister[0] , %unknown, 0 },
460 { ExprConstant[0] , 1, ExprSize8 },
461 { ExprConstant[0] , 0x20070f, ExprSize32 | ExprSignedHex },
462 };
463 0000000000000000: a0 88 77 66 55 44 33 22 11 mov %al, [0x11223 34455667788]
464 a0 386 OpcodeHasImmed_Addr OperandSize_b
465 Mov %al, $Ob
466 RegAL OpSet
467 O_Operand OpUse
468 NaClExpVector[8] = {
469 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
470 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
471 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
472 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
473 { ExprRegister[0] , %unknown, 0 },
474 { ExprRegister[0] , %unknown, 0 },
475 { ExprConstant[0] , 1, ExprSize8 },
476 { ExprConstant[0] , 0x1122334455667788, ExprSize64 | ExprUnsignedHex },
477 };
478 0000000000000000: 66 a1 88 77 66 55 44 33 22 11 mov %ax, [0x11223 34455667788]
479 a1 386 OpcodeHasImmed_Addr OpcodeAllowsData16 Operand Size_w OperandSize_v OperandSize_o
480 Mov $rAXv, $Ov
481 RegREAX OpSet OperandZeroExtends_v
482 O_Operand OpUse
483 NaClExpVector[8] = {
484 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
485 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
486 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
487 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
488 { ExprRegister[0] , %unknown, 0 },
489 { ExprRegister[0] , %unknown, 0 },
490 { ExprConstant[0] , 1, ExprSize8 },
491 { ExprConstant[0] , 0x1122334455667788, ExprSize64 | ExprUnsignedHex },
492 };
493 0000000000000000: a2 88 77 66 55 44 33 22 11 mov [0x1122334455 667788], %al
494 a2 386 OpcodeHasImmed_Addr OperandSize_b
495 Mov $Ob, %al
496 O_Operand OpSet
497 RegAL OpUse
498 NaClExpVector[8] = {
499 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
500 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
501 { ExprRegister[0] , %unknown, 0 },
502 { ExprRegister[0] , %unknown, 0 },
503 { ExprConstant[0] , 1, ExprSize8 },
504 { ExprConstant[0] , 0x1122334455667788, ExprSize64 | ExprUnsignedHex },
505 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
506 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
507 };
508 0000000000000000: 66 a3 88 77 66 55 44 33 22 11 mov [0x1122334455 667788], %ax
509 a3 386 OpcodeHasImmed_Addr OpcodeAllowsData16 Operand Size_w OperandSize_v OperandSize_o
510 Mov $Ov, $rAXv
511 O_Operand OpSet OperandZeroExtends_v
512 RegREAX OpUse
513 NaClExpVector[8] = {
514 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
515 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
516 { ExprRegister[0] , %unknown, 0 },
517 { ExprRegister[0] , %unknown, 0 },
518 { ExprConstant[0] , 1, ExprSize8 },
519 { ExprConstant[0] , 0x1122334455667788, ExprSize64 | ExprUnsignedHex },
520 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
521 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
522 };
523 0000000000000000: 48 b8 88 77 66 55 44 33 22 11 mov %rax, 0x11223 34455667788
524 b8 - r0 386 OpcodeHasImmed OpcodePlusR OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
525 Mov $r8v, $Iv
526 G_OpcodeBase OpSet OperandZeroExtends_v
527 I_Operand OpUse
528 NaClExpVector[4] = {
529 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
530 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
531 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
532 { ExprConstant[0] , 0x1122334455667788, ExprUsed | ExprSize64 | ExprUnsignedHe x },
533 };
534 0000000000000000: 44 8a 04 00 mov %r8b, [%rax+% rax*1]
535 8a 386 OpcodeUsesModRm OperandSize_b
536 Mov $Gb, $Eb
537 G_Operand OpSet
538 E_Operand OpUse
539 NaClExpVector[8] = {
540 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
541 { ExprRegister[0] , %r8b, ExprSet | ExprSize8 },
542 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
543 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
544 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
545 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
546 { ExprConstant[0] , 1, ExprSize8 },
547 { ExprConstant[0] , 0, ExprSize8 },
548 };
549 0000000000000000: 8a 44 05 00 mov %al, [%rbp+%r ax*1]
550 8a 386 OpcodeUsesModRm OperandSize_b
551 Mov $Gb, $Eb
552 G_Operand OpSet
553 E_Operand OpUse
554 NaClExpVector[8] = {
555 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
556 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
557 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
558 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
559 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
560 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
561 { ExprConstant[0] , 1, ExprSize8 },
562 { ExprConstant[0] , 0x0, ExprSize8 | ExprSignedHex },
563 };
564 0000000000000000: 42 8a 04 20 mov %al, [%rax+%r 12*1]
565 8a 386 OpcodeUsesModRm OperandSize_b
566 Mov $Gb, $Eb
567 G_Operand OpSet
568 E_Operand OpUse
569 NaClExpVector[8] = {
570 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
571 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
572 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
573 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
574 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
575 { ExprRegister[0] , %r12, ExprUsed | ExprSize64 },
576 { ExprConstant[0] , 1, ExprSize8 },
577 { ExprConstant[0] , 0, ExprSize8 },
578 };
579 0000000000000000: 41 8a 44 05 00 mov %al, [%r13+%r ax*1]
580 8a 386 OpcodeUsesModRm OperandSize_b
581 Mov $Gb, $Eb
582 G_Operand OpSet
583 E_Operand OpUse
584 NaClExpVector[8] = {
585 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
586 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
587 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
588 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
589 { ExprRegister[0] , %r13, ExprUsed | ExprSize64 },
590 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
591 { ExprConstant[0] , 1, ExprSize8 },
592 { ExprConstant[0] , 0x0, ExprSize8 | ExprSignedHex },
593 };
594 0000000000000000: 0f 38 08 2c 25 00 00 00 00 psignb %mmx5, [0x 0]
595 0f 38 08 SSSE3 OpcodeUsesModRm
596 Psignb $Pq, $Qq
597 Mmx_G_Operand OpUse OpSet
598 Mmx_E_Operand OpUse
599 NaClExpVector[8] = {
600 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
601 { ExprRegister[0] , %mmx5, ExprSet | ExprUsed },
602 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
603 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
604 { ExprRegister[0] , %unknown, 0 },
605 { ExprRegister[0] , %unknown, 0 },
606 { ExprConstant[0] , 1, ExprSize8 },
607 { ExprConstant[0] , 0x0, ExprSize32 | ExprSignedHex },
608 };
609 0000000000000000: 66 0f 38 08 2c 25 00 00 00 00 psignb %xmm5, [0x 0]
610 66 0f 38 08 SSSE3 OpcodeUsesModRm OpcodeAllowsData16 SizeIgnor esData16
611 Psignb $Vdq, $Wdq
612 Xmm_G_Operand OpUse OpSet
613 Xmm_E_Operand OpUse
614 NaClExpVector[8] = {
615 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
616 { ExprRegister[0] , %xmm5, ExprSet | ExprUsed },
617 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
618 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
619 { ExprRegister[0] , %unknown, 0 },
620 { ExprRegister[0] , %unknown, 0 },
621 { ExprConstant[0] , 1, ExprSize8 },
622 { ExprConstant[0] , 0x0, ExprSize32 | ExprSignedHex },
623 };
624 0000000000000000: 66 44 0f 38 08 2c 00 psignb %xmm13, [% rax+%rax*1]
625 66 0f 38 08 SSSE3 OpcodeUsesModRm OpcodeAllowsData16 SizeIgnor esData16
626 Psignb $Vdq, $Wdq
627 Xmm_G_Operand OpUse OpSet
628 Xmm_E_Operand OpUse
629 NaClExpVector[8] = {
630 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
631 { ExprRegister[0] , %xmm13, ExprSet | ExprUsed },
632 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
633 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
634 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
635 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
636 { ExprConstant[0] , 1, ExprSize8 },
637 { ExprConstant[0] , 0, ExprSize8 },
638 };
639 0000000000000000: dd 24 00 frstor [%rax+%rax *1]
640 dd / 4 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm
641 Frstor $Mf
642 M_Operand OpUse
643 NaClExpVector[6] = {
644 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
645 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
646 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
647 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
648 { ExprConstant[0] , 1, ExprSize8 },
649 { ExprConstant[0] , 0, ExprSize8 },
650 };
651 0000000000000000: 67 dd 24 00 frstor [%eax+%eax *1]
652 dd / 4 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm
653 Frstor $Mf
654 M_Operand OpUse
655 NaClExpVector[6] = {
656 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
657 { ExprMemOffset[4] , 0, ExprUsed | ExprSize32 },
658 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
659 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
660 { ExprConstant[0] , 1, ExprSize8 },
661 { ExprConstant[0] , 0, ExprSize8 },
662 };
663 0000000000000000: dc c1 fadd %st1, %st0
664 dc c1 X87
665 Fadd %st1, %st0
666 RegST1 OpUse OpSet
667 RegST0 OpUse
668 NaClExpVector[4] = {
669 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
670 { ExprRegister[0] , %st1, ExprSet | ExprUsed },
671 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
672 { ExprRegister[0] , %st0, ExprUsed },
673 };
674 0000000000000000: d8 74 24 10 fdiv %st0, [%rsp+ 0x10]
675 d8 / 6 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm
676 Fdiv %st0, $Md
677 RegST0 OpUse OpSet
678 Mv_Operand OpUse
679 NaClExpVector[8] = {
680 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
681 { ExprRegister[0] , %st0, ExprSet | ExprUsed },
682 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
683 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
684 { ExprRegister[0] , %rsp, ExprUsed | ExprSize64 },
685 { ExprRegister[0] , %unknown, 0 },
686 { ExprConstant[0] , 1, ExprSize8 },
687 { ExprConstant[0] , 0x10, ExprSize8 | ExprSignedHex },
688 };
689 0000000000000000: 67 d8 74 24 10 fdiv %st0, [%esp+ 0x10]
690 d8 / 6 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm
691 Fdiv %st0, $Md
692 RegST0 OpUse OpSet
693 Mv_Operand OpUse
694 NaClExpVector[8] = {
695 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
696 { ExprRegister[0] , %st0, ExprSet | ExprUsed },
697 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
698 { ExprMemOffset[4] , 0, ExprUsed | ExprSize32 },
699 { ExprRegister[0] , %esp, ExprUsed | ExprSize32 },
700 { ExprRegister[0] , %unknown, 0 },
701 { ExprConstant[0] , 1, ExprSize8 },
702 { ExprConstant[0] , 0x10, ExprSize8 | ExprSignedHex },
703 };
704 0000000000000000: dc 44 00 04 fadd %st0, [%rax+ %rax*1+0x4]
705 dc / 0 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm
706 Fadd %st0, $Mq
707 RegST0 OpUse OpSet
708 Mo_Operand OpUse
709 NaClExpVector[8] = {
710 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
711 { ExprRegister[0] , %st0, ExprSet | ExprUsed },
712 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
713 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
714 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
715 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
716 { ExprConstant[0] , 1, ExprSize8 },
717 { ExprConstant[0] , 0x4, ExprSize8 | ExprSignedHex },
718 };
719 0000000000000000: da 04 25 04 00 00 00 fiadd %st0, [0x4]
720 da / 0 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm
721 Fiadd %st0, $Md
722 RegST0 OpUse OpSet
723 Mv_Operand OpUse
724 NaClExpVector[8] = {
725 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
726 { ExprRegister[0] , %st0, ExprSet | ExprUsed },
727 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
728 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
729 { ExprRegister[0] , %unknown, 0 },
730 { ExprRegister[0] , %unknown, 0 },
731 { ExprConstant[0] , 1, ExprSize8 },
732 { ExprConstant[0] , 0x4, ExprSize32 | ExprSignedHex },
733 };
734 0000000000000000: da 70 04 fidiv %st0, [%rax +0x4]
735 da / 6 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm
736 Fidiv %st0, $Md
737 RegST0 OpUse OpSet
738 Mv_Operand OpUse
739 NaClExpVector[8] = {
740 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
741 { ExprRegister[0] , %st0, ExprSet | ExprUsed },
742 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
743 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
744 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
745 { ExprRegister[0] , %unknown, 0 },
746 { ExprConstant[0] , 1, ExprSize8 },
747 { ExprConstant[0] , 0x4, ExprSize8 | ExprSignedHex },
748 };
749 0000000000000000: de 50 04 ficom %st0, [%rax +0x4]
750 de / 2 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm
751 Ficom %st0, $Mw
752 RegST0 OpUse
753 Mw_Operand OpUse
754 NaClExpVector[8] = {
755 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
756 { ExprRegister[0] , %st0, ExprUsed },
757 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
758 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
759 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
760 { ExprRegister[0] , %unknown, 0 },
761 { ExprConstant[0] , 1, ExprSize8 },
762 { ExprConstant[0] , 0x4, ExprSize8 | ExprSignedHex },
763 };
764 0000000000000000: dc e5 fsubr %st5, %st0
765 dc e5 X87
766 Fsubr %st5, %st0
767 RegST5 OpUse OpSet
768 RegST0 OpUse
769 NaClExpVector[4] = {
770 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
771 { ExprRegister[0] , %st5, ExprSet | ExprUsed },
772 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
773 { ExprRegister[0] , %st0, ExprUsed },
774 };
775 0000000000000000: dc f3 fdivr %st3, %st0
776 dc f3 X87
777 Fdivr %st3, %st0
778 RegST3 OpUse OpSet
779 RegST0 OpUse
780 NaClExpVector[4] = {
781 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
782 { ExprRegister[0] , %st3, ExprSet | ExprUsed },
783 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
784 { ExprRegister[0] , %st0, ExprUsed },
785 };
786 0000000000000000: dc ea fsub %st2, %st0
787 dc ea X87
788 Fsub %st2, %st0
789 RegST2 OpUse OpSet
790 RegST0 OpUse
791 NaClExpVector[4] = {
792 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
793 { ExprRegister[0] , %st2, ExprSet | ExprUsed },
794 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
795 { ExprRegister[0] , %st0, ExprUsed },
796 };
797 0000000000000000: dc ce fmul %st6, %st0
798 dc ce X87
799 Fmul %st6, %st0
800 RegST6 OpUse OpSet
801 RegST0 OpUse
802 NaClExpVector[4] = {
803 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
804 { ExprRegister[0] , %st6, ExprSet | ExprUsed },
805 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
806 { ExprRegister[0] , %st0, ExprUsed },
807 };
808 0000000000000000: 48 63 c6 movsxd %rax, %esi
809 63 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o LongMode
810 Movsxd $Gv, $Ed
811 G_Operand OpSet OperandZeroExtends_v
812 Ev_Operand OpUse
813 NaClExpVector[4] = {
814 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
815 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
816 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
817 { ExprRegister[0] , %esi, ExprUsed | ExprSize32 },
818 };
819 0000000000000000: 63 c6 movsxd %eax, %esi
820 63 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o LongMode
821 Movsxd $Gv, $Ed
822 G_Operand OpSet OperandZeroExtends_v
823 Ev_Operand OpUse
824 NaClExpVector[4] = {
825 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
826 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
827 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
828 { ExprRegister[0] , %esi, ExprUsed | ExprSize32 },
829 };
830 0000000000000000: 6c insb
831 6c 386 OpcodeAllowsRep OperandSize_b NaClIllegal
832 Insb {$Yb}, {%dx}
833 RegES_EDI OpSet OpImplicit
834 RegDX OpUse OpImplicit
835 NaClExpVector[6] = {
836 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
837 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
838 { ExprRegister[0] , %es, ExprSize16 },
839 { ExprRegister[0] , %rdi, ExprSize64 },
840 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
841 { ExprRegister[0] , %dx, ExprUsed | ExprSize16 },
842 };
843 0000000000000000: 6d insd
844 6d 386 OpcodeAllowsRep OperandSize_v OperandSize_o Na ClIllegal
845 Insd {$Yzd}, {%dx}
846 RegES_EDI OpSet OpImplicit
847 RegDX OpUse OpImplicit
848 NaClExpVector[6] = {
849 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
850 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
851 { ExprRegister[0] , %es, ExprSize16 },
852 { ExprRegister[0] , %rdi, ExprSize64 },
853 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
854 { ExprRegister[0] , %dx, ExprUsed | ExprSize16 },
855 };
856 0000000000000000: 66 6d insw
857 6d 386 OpcodeAllowsRep OpcodeAllowsData16 OperandSize _w NaClIllegal
858 Insw {$Yzw}, {%dx}
859 RegES_EDI OpSet OpImplicit
860 RegDX OpUse OpImplicit
861 NaClExpVector[6] = {
862 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
863 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
864 { ExprRegister[0] , %es, ExprSize16 },
865 { ExprRegister[0] , %rdi, ExprSize64 },
866 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
867 { ExprRegister[0] , %dx, ExprUsed | ExprSize16 },
868 };
869 0000000000000000: 6e outsb
870 6e 386 OpcodeAllowsRep OperandSize_b NaClIllegal
871 Outsb {%dx}, {$Xb}
872 RegDX OpUse OpImplicit
873 RegDS_ESI OpUse OpImplicit
874 NaClExpVector[6] = {
875 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
876 { ExprRegister[0] , %dx, ExprUsed | ExprSize16 },
877 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
878 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
879 { ExprRegister[0] , %ds, ExprSize16 },
880 { ExprRegister[0] , %rsi, ExprSize64 },
881 };
882 0000000000000000: 6f outsd
883 6f 386 OpcodeAllowsRep OperandSize_v OperandSize_o Na ClIllegal
884 Outsd {%dx}, {$Xzd}
885 RegDX OpUse OpImplicit
886 RegDS_ESI OpUse OpImplicit
887 NaClExpVector[6] = {
888 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
889 { ExprRegister[0] , %dx, ExprUsed | ExprSize16 },
890 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
891 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
892 { ExprRegister[0] , %ds, ExprSize16 },
893 { ExprRegister[0] , %rsi, ExprSize64 },
894 };
895 0000000000000000: 66 6f outsw
896 6f 386 OpcodeAllowsRep OpcodeAllowsData16 OperandSize _w NaClIllegal
897 Outsw {%dx}, {$Xzw}
898 RegDX OpUse OpImplicit
899 RegDS_ESI OpUse OpImplicit
900 NaClExpVector[6] = {
901 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
902 { ExprRegister[0] , %dx, ExprUsed | ExprSize16 },
903 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
904 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
905 { ExprRegister[0] , %ds, ExprSize16 },
906 { ExprRegister[0] , %rsi, ExprSize64 },
907 };
908 0000000000000000: 66 98 cbw
909 98 386 OpcodeAllowsData16 OperandSize_w
910 Cbw {%ax}, {%al}
911 RegAX OpSet OpImplicit
912 RegAL OpUse OpImplicit
913 NaClExpVector[4] = {
914 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
915 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
916 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
917 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
918 };
919 0000000000000000: 98 cwde
920 98 386 OperandSize_v
921 Cwde {%eax}, {%ax}
922 RegEAX OpSet OpImplicit OperandSignExtends_v
923 RegAX OpUse OpImplicit
924 NaClExpVector[4] = {
925 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
926 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
927 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
928 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
929 };
930 0000000000000000: 48 98 cdqe
931 98 386 OperandSize_o LongMode
932 Cdqe {%rax}, {%eax}
933 RegRAX OpSet OpImplicit
934 RegEAX OpUse OpImplicit
935 NaClExpVector[4] = {
936 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
937 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
938 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
939 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
940 };
941 0000000000000000: 66 99 cwd
942 99 386 OpcodeAllowsData16 OperandSize_w
943 Cwd {%dx}, {%ax}
944 RegDX OpSet OpImplicit
945 RegAX OpUse OpImplicit
946 NaClExpVector[4] = {
947 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
948 { ExprRegister[0] , %dx, ExprSet | ExprSize16 },
949 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
950 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
951 };
952 0000000000000000: 99 cdq
953 99 386 OperandSize_v
954 Cdq {%edx}, {%eax}
955 RegEDX OpSet OpImplicit
956 RegEAX OpUse OpImplicit
957 NaClExpVector[4] = {
958 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
959 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
960 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
961 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
962 };
963 0000000000000000: 48 99 cqo
964 99 386 OperandSize_o LongMode
965 Cqo {%rdx}, {%rax}
966 RegRDX OpSet OpImplicit
967 RegRAX OpUse OpImplicit
968 NaClExpVector[4] = {
969 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
970 { ExprRegister[0] , %rdx, ExprSet | ExprSize64 },
971 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
972 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
973 };
974 0000000000000000: 86 c2 xchg %dl, %al
975 86 386 OpcodeUsesModRm OpcodeLockable OperandSize_b
976 Xchg $Eb, $Gb
977 E_Operand OpUse OpSet
978 G_Operand OpUse OpSet
979 NaClExpVector[4] = {
980 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
981 { ExprRegister[0] , %dl, ExprSet | ExprUsed | ExprSize8 },
982 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
983 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
984 };
985 0000000000000000: 86 40 20 xchg [%rax+0x20], %al
986 86 386 OpcodeUsesModRm OpcodeLockable OperandSize_b
987 Xchg $Eb, $Gb
988 E_Operand OpUse OpSet
989 G_Operand OpUse OpSet
990 NaClExpVector[8] = {
991 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
992 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
993 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
994 { ExprRegister[0] , %unknown, 0 },
995 { ExprConstant[0] , 1, ExprSize8 },
996 { ExprConstant[0] , 0x20, ExprSize8 | ExprSignedHex },
997 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
998 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
999 };
1000 0000000000000000: 87 40 20 xchg [%rax+0x20], %eax
1001 87 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
1002 Xchg $Ev, $Gv
1003 E_Operand OpUse OpSet OperandZeroExtends_v
1004 G_Operand OpUse OpSet OperandZeroExtends_v
1005 NaClExpVector[8] = {
1006 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1007 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
1008 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
1009 { ExprRegister[0] , %unknown, 0 },
1010 { ExprConstant[0] , 1, ExprSize8 },
1011 { ExprConstant[0] , 0x20, ExprSize8 | ExprSignedHex },
1012 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1013 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1014 };
1015 0000000000000000: a6 cmpsb [%rdi], [%r si]
1016 a6 386 OpcodeAllowsRep OpcodeAllowsRepne OperandSize_ b
1017 Cmpsb $Yb, $Xb
1018 RegES_EDI OpUse
1019 RegDS_ESI OpUse
1020 NaClExpVector[8] = {
1021 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1022 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
1023 { ExprRegister[0] , %es, ExprSize16 },
1024 { ExprRegister[0] , %rdi, ExprSize64 },
1025 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1026 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1027 { ExprRegister[0] , %ds, ExprSize16 },
1028 { ExprRegister[0] , %rsi, ExprSize64 },
1029 };
1030 0000000000000000: 66 a7 cmpsw [%rdi], [%r si]
1031 a7 386 OpcodeAllowsRep OpcodeAllowsRepne OpcodeAllows Data16 OperandSize_w
1032 Cmpsw $Yvw, $Xvw
1033 RegES_EDI OpUse
1034 RegDS_ESI OpUse
1035 NaClExpVector[8] = {
1036 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1037 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
1038 { ExprRegister[0] , %es, ExprSize16 },
1039 { ExprRegister[0] , %rdi, ExprSize64 },
1040 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1041 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1042 { ExprRegister[0] , %ds, ExprSize16 },
1043 { ExprRegister[0] , %rsi, ExprSize64 },
1044 };
1045 0000000000000000: a7 cmpsd [%rdi], [%r si]
1046 a7 386 OpcodeAllowsRep OpcodeAllowsRepne OperandSize_ v
1047 Cmpsd $Yvd, $Xvd
1048 RegES_EDI OpUse
1049 RegDS_ESI OpUse
1050 NaClExpVector[8] = {
1051 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1052 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
1053 { ExprRegister[0] , %es, ExprSize16 },
1054 { ExprRegister[0] , %rdi, ExprSize64 },
1055 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1056 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1057 { ExprRegister[0] , %ds, ExprSize16 },
1058 { ExprRegister[0] , %rsi, ExprSize64 },
1059 };
1060 0000000000000000: 48 a7 cmpsq [%rdi], [%r si]
1061 a7 386 OpcodeAllowsRep OpcodeAllowsRepne OperandSize_ o LongMode
1062 Cmpsq $Yvq, $Xvq
1063 RegES_EDI OpUse
1064 RegDS_ESI OpUse
1065 NaClExpVector[8] = {
1066 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1067 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
1068 { ExprRegister[0] , %es, ExprSize16 },
1069 { ExprRegister[0] , %rdi, ExprSize64 },
1070 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1071 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1072 { ExprRegister[0] , %ds, ExprSize16 },
1073 { ExprRegister[0] , %rsi, ExprSize64 },
1074 };
1075 0000000000000000: aa stosb [%rdi]
1076 aa 386 OpcodeAllowsRep OperandSize_b
1077 Stosb $Yb, {%al}
1078 RegES_EDI OpSet
1079 RegAL OpUse OpImplicit
1080 NaClExpVector[6] = {
1081 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1082 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
1083 { ExprRegister[0] , %es, ExprSize16 },
1084 { ExprRegister[0] , %rdi, ExprSize64 },
1085 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1086 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
1087 };
1088 0000000000000000: ab stosd [%rdi]
1089 ab 386 OpcodeAllowsRep OperandSize_v
1090 Stosd $Yvd, {$rAXvd}
1091 RegES_EDI OpSet
1092 RegEAX OpUse OpImplicit
1093 NaClExpVector[6] = {
1094 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1095 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
1096 { ExprRegister[0] , %es, ExprSize16 },
1097 { ExprRegister[0] , %rdi, ExprSize64 },
1098 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1099 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
1100 };
1101 0000000000000000: 66 ab stosw [%rdi]
1102 ab 386 OpcodeAllowsRep OpcodeAllowsData16 OperandSize _w
1103 Stosw $Yvw, {$rAXvw}
1104 RegES_EDI OpSet
1105 RegAX OpUse OpImplicit
1106 NaClExpVector[6] = {
1107 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1108 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
1109 { ExprRegister[0] , %es, ExprSize16 },
1110 { ExprRegister[0] , %rdi, ExprSize64 },
1111 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1112 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
1113 };
1114 0000000000000000: 48 ab stosq [%rdi]
1115 ab 386 OpcodeAllowsRep OperandSize_o LongMode
1116 Stosq $Yvq, {$rAXvq}
1117 RegES_EDI OpSet
1118 RegRAX OpUse OpImplicit
1119 NaClExpVector[6] = {
1120 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1121 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
1122 { ExprRegister[0] , %es, ExprSize16 },
1123 { ExprRegister[0] , %rdi, ExprSize64 },
1124 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1125 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
1126 };
1127 0000000000000000: a4 movsb [%rdi], [%r si]
1128 a4 386 OpcodeAllowsRep OperandSize_b
1129 Movsb $Yb, $Xb
1130 RegES_EDI OpSet
1131 RegDS_ESI OpUse
1132 NaClExpVector[8] = {
1133 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1134 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
1135 { ExprRegister[0] , %es, ExprSize16 },
1136 { ExprRegister[0] , %rdi, ExprSize64 },
1137 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1138 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1139 { ExprRegister[0] , %ds, ExprSize16 },
1140 { ExprRegister[0] , %rsi, ExprSize64 },
1141 };
1142 0000000000000000: 66 a5 movsw [%rdi], [%r si]
1143 a5 386 OpcodeAllowsRep OpcodeAllowsData16 OperandSize _w
1144 Movsw $Yvw, $Xvw
1145 RegES_EDI OpSet
1146 RegDS_ESI OpUse
1147 NaClExpVector[8] = {
1148 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1149 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
1150 { ExprRegister[0] , %es, ExprSize16 },
1151 { ExprRegister[0] , %rdi, ExprSize64 },
1152 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1153 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1154 { ExprRegister[0] , %ds, ExprSize16 },
1155 { ExprRegister[0] , %rsi, ExprSize64 },
1156 };
1157 0000000000000000: a5 movsd [%rdi], [%r si]
1158 a5 386 OpcodeAllowsRep OperandSize_v
1159 Movsd $Yvd, $Xvd
1160 RegES_EDI OpSet
1161 RegDS_ESI OpUse
1162 NaClExpVector[8] = {
1163 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1164 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
1165 { ExprRegister[0] , %es, ExprSize16 },
1166 { ExprRegister[0] , %rdi, ExprSize64 },
1167 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1168 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1169 { ExprRegister[0] , %ds, ExprSize16 },
1170 { ExprRegister[0] , %rsi, ExprSize64 },
1171 };
1172 0000000000000000: 48 a5 movsq [%rdi], [%r si]
1173 a5 386 OpcodeAllowsRep OperandSize_o LongMode
1174 Movsq $Yvq, $Xvq
1175 RegES_EDI OpSet
1176 RegDS_ESI OpUse
1177 NaClExpVector[8] = {
1178 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1179 { ExprSegmentAddress[2] , 0, ExprSet | ExprSize64 | ExprESrCase },
1180 { ExprRegister[0] , %es, ExprSize16 },
1181 { ExprRegister[0] , %rdi, ExprSize64 },
1182 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1183 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1184 { ExprRegister[0] , %ds, ExprSize16 },
1185 { ExprRegister[0] , %rsi, ExprSize64 },
1186 };
1187 0000000000000000: 9c pushfq
1188 9c 386 OperandSize_o NaClIllegal OperandSizeDefaultIs 64 LongMode
1189 Pushfq {%rsp}, {$Fvq}
1190 RegRSP OpUse OpSet OpImplicit
1191 RegRFLAGS OpUse OpImplicit
1192 NaClExpVector[4] = {
1193 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1194 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
1195 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1196 { ExprRegister[0] , %rflags, ExprUsed },
1197 };
1198 0000000000000000: 9d popfq
1199 9d 386 OperandSize_o NaClIllegal OperandSizeDefaultIs 64 LongMode
1200 Popfq {%rsp}, {$Fvq}
1201 RegRSP OpUse OpSet OpImplicit
1202 RegRFLAGS OpSet OpImplicit
1203 NaClExpVector[4] = {
1204 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1205 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
1206 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1207 { ExprRegister[0] , %rflags, ExprSet },
1208 };
1209 0000000000000000: ac lodsb [%rsi]
1210 ac 386 OpcodeAllowsRep OperandSize_b
1211 Lodsb {%al}, $Xb
1212 RegAL OpSet OpImplicit
1213 RegDS_ESI OpUse
1214 NaClExpVector[6] = {
1215 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1216 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
1217 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1218 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1219 { ExprRegister[0] , %ds, ExprSize16 },
1220 { ExprRegister[0] , %rsi, ExprSize64 },
1221 };
1222 0000000000000000: ad lodsd [%rsi]
1223 ad 386 OpcodeAllowsRep OperandSize_v
1224 Lodsd {$rAXvd}, $Xvd
1225 RegEAX OpSet OpImplicit
1226 RegDS_ESI OpUse
1227 NaClExpVector[6] = {
1228 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1229 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
1230 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1231 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1232 { ExprRegister[0] , %ds, ExprSize16 },
1233 { ExprRegister[0] , %rsi, ExprSize64 },
1234 };
1235 0000000000000000: 66 ad lodsw [%rsi]
1236 ad 386 OpcodeAllowsRep OpcodeAllowsData16 OperandSize _w
1237 Lodsw {$rAXvw}, $Xvw
1238 RegAX OpSet OpImplicit
1239 RegDS_ESI OpUse
1240 NaClExpVector[6] = {
1241 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1242 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
1243 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1244 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1245 { ExprRegister[0] , %ds, ExprSize16 },
1246 { ExprRegister[0] , %rsi, ExprSize64 },
1247 };
1248 0000000000000000: 48 ad lodsq [%rsi]
1249 ad 386 OpcodeAllowsRep OperandSize_o LongMode
1250 Lodsq {$rAXvq}, $Xvq
1251 RegRAX OpSet OpImplicit
1252 RegDS_ESI OpUse
1253 NaClExpVector[6] = {
1254 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1255 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
1256 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1257 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
1258 { ExprRegister[0] , %ds, ExprSize16 },
1259 { ExprRegister[0] , %rsi, ExprSize64 },
1260 };
1261 0000000000000000: ae scasb [%rdi]
1262 ae 386 OpcodeAllowsRep OpcodeAllowsRepne OperandSize_ b
1263 Scasb {%al}, $Yb
1264 RegAL OpUse OpImplicit
1265 RegES_EDI OpUse
1266 NaClExpVector[6] = {
1267 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1268 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
1269 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1270 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
1271 { ExprRegister[0] , %es, ExprSize16 },
1272 { ExprRegister[0] , %rdi, ExprSize64 },
1273 };
1274 0000000000000000: af scasd [%rdi]
1275 af 386 OpcodeAllowsRep OpcodeAllowsRepne OperandSize_ v
1276 Scasd {$rAXvd}, $Yvd
1277 RegEAX OpUse OpImplicit
1278 RegES_EDI OpUse
1279 NaClExpVector[6] = {
1280 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1281 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
1282 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1283 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
1284 { ExprRegister[0] , %es, ExprSize16 },
1285 { ExprRegister[0] , %rdi, ExprSize64 },
1286 };
1287 0000000000000000: 66 af scasw [%rdi]
1288 af 386 OpcodeAllowsRep OpcodeAllowsRepne OpcodeAllows Data16 OperandSize_w
1289 Scasw {$rAXvw}, $Yvw
1290 RegAX OpUse OpImplicit
1291 RegES_EDI OpUse
1292 NaClExpVector[6] = {
1293 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1294 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
1295 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1296 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
1297 { ExprRegister[0] , %es, ExprSize16 },
1298 { ExprRegister[0] , %rdi, ExprSize64 },
1299 };
1300 0000000000000000: 48 af scasq [%rdi]
1301 af 386 OpcodeAllowsRep OpcodeAllowsRepne OperandSize_ o LongMode
1302 Scasq {$rAXvq}, $Yvq
1303 RegRAX OpUse OpImplicit
1304 RegES_EDI OpUse
1305 NaClExpVector[6] = {
1306 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1307 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
1308 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1309 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprESrCase },
1310 { ExprRegister[0] , %es, ExprSize16 },
1311 { ExprRegister[0] , %rdi, ExprSize64 },
1312 };
1313 0000000000000000: c8 2c 01 00 enter 0x12c, 0x0
1314 c8 386 OpcodeHasImmed_w OpcodeHasImmed2_b NaClIllegal OperandSizeDefaultIs64
1315 Enter {%rsp}, {%rbp}, $Iw, $I2b
1316 RegRSP OpUse OpSet OpImplicit
1317 RegRBP OpUse OpSet OpImplicit
1318 I_Operand OpUse
1319 I2_Operand OpUse
1320 NaClExpVector[8] = {
1321 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1322 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
1323 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1324 { ExprRegister[0] , %rbp, ExprSet | ExprUsed | ExprSize64 },
1325 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1326 { ExprConstant[0] , 0x12c, ExprUsed | ExprSize16 | ExprUnsignedHex },
1327 { OperandReference[1] , 3, ExprSize8 | ExprUnsignedInt },
1328 { ExprConstant[0] , 0x0, ExprUsed | ExprSize8 | ExprUnsignedHex },
1329 };
1330 0000000000000000: 80 e4 df and %ah, 0xdf
1331 80 / 4 386 OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed O pcodeLockable OperandSize_b
1332 And $Eb, $Ib
1333 E_Operand OpUse OpSet
1334 I_Operand OpUse
1335 NaClExpVector[4] = {
1336 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1337 { ExprRegister[0] , %ah, ExprSet | ExprUsed | ExprSize8 },
1338 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1339 { ExprConstant[0] , 0xdf, ExprUsed | ExprSize8 | ExprUnsignedHex },
1340 };
1341 0000000000000000: 22 24 25 df 00 00 00 and %ah, [0xdf]
1342 22 386 OpcodeUsesModRm OpcodeLockable OperandSize_b
1343 And $Gb, $Eb
1344 G_Operand OpUse OpSet
1345 E_Operand OpUse
1346 NaClExpVector[8] = {
1347 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1348 { ExprRegister[0] , %ah, ExprSet | ExprUsed | ExprSize8 },
1349 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1350 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1351 { ExprRegister[0] , %unknown, 0 },
1352 { ExprRegister[0] , %unknown, 0 },
1353 { ExprConstant[0] , 1, ExprSize8 },
1354 { ExprConstant[0] , 0xdf, ExprSize32 | ExprSignedHex },
1355 };
1356 0000000000000000: 40 22 24 25 df 00 00 00 and %spl, [0xdf]
1357 22 386 OpcodeUsesModRm OpcodeLockable OperandSize_b
1358 And $Gb, $Eb
1359 G_Operand OpUse OpSet
1360 E_Operand OpUse
1361 NaClExpVector[8] = {
1362 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1363 { ExprRegister[0] , %spl, ExprSet | ExprUsed | ExprSize8 },
1364 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1365 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1366 { ExprRegister[0] , %unknown, 0 },
1367 { ExprRegister[0] , %unknown, 0 },
1368 { ExprConstant[0] , 1, ExprSize8 },
1369 { ExprConstant[0] , 0xdf, ExprSize32 | ExprSignedHex },
1370 };
1371 0000000000000000: 8d 04 85 ff ff ff ff lea %eax, [%rax*4 -0x1]
1372 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
1373 Lea $Gv, $M
1374 G_Operand OpSet OperandZeroExtends_v
1375 M_Operand OpAddress
1376 NaClExpVector[8] = {
1377 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1378 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
1379 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1380 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
1381 { ExprRegister[0] , %unknown, 0 },
1382 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
1383 { ExprConstant[0] , 4, ExprSize8 },
1384 { ExprConstant[0] , -0x1, ExprSize32 | ExprSignedHex },
1385 };
1386 0000000000000000: 64 48 33 14 25 28 00 00 00 xor %rdx, %fs:[0x 28]
1387 33 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
1388 Xor $Gv, $Ev
1389 G_Operand OpUse OpSet OperandZeroExtends_v
1390 E_Operand OpUse
1391 NaClExpVector[10] = {
1392 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1393 { ExprRegister[0] , %rdx, ExprSet | ExprUsed | ExprSize64 },
1394 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1395 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 },
1396 { ExprRegister[0] , %fs, ExprUsed | ExprSize16 },
1397 { ExprMemOffset[4] , 0, ExprSize64 },
1398 { ExprRegister[0] , %unknown, 0 },
1399 { ExprRegister[0] , %unknown, 0 },
1400 { ExprConstant[0] , 1, ExprSize8 },
1401 { ExprConstant[0] , 0x28, ExprSize32 | ExprSignedHex },
1402 };
1403 0000000000000000: 48 b8 cd cc cc cc cc cc cc cc mov %rax, 0xccccc ccccccccccd
1404 b8 - r0 386 OpcodeHasImmed OpcodePlusR OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
1405 Mov $r8v, $Iv
1406 G_OpcodeBase OpSet OperandZeroExtends_v
1407 I_Operand OpUse
1408 NaClExpVector[4] = {
1409 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1410 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
1411 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1412 { ExprConstant[0] , 0xcccccccccccccccd, ExprUsed | ExprSize64 | ExprUnsignedHe x },
1413 };
1414 0000000000000000: 66 6b c0 16 imul %ax, %ax, 0x 16
1415 6b 386 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsD ata16 OperandSize_w OperandSize_v OperandSize_o
1416 Imul $Gv, $Ev, $Ib
1417 G_Operand OpSet OperandZeroExtends_v
1418 E_Operand OpUse
1419 I_Operand OpUse
1420 NaClExpVector[6] = {
1421 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1422 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
1423 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1424 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
1425 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1426 { ExprConstant[0] , 0x16, ExprUsed | ExprSize8 | ExprUnsignedHex },
1427 };
1428 0000000000000000: 66 6b d8 16 imul %bx, %ax, 0x 16
1429 6b 386 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsD ata16 OperandSize_w OperandSize_v OperandSize_o
1430 Imul $Gv, $Ev, $Ib
1431 G_Operand OpSet OperandZeroExtends_v
1432 E_Operand OpUse
1433 I_Operand OpUse
1434 NaClExpVector[6] = {
1435 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1436 { ExprRegister[0] , %bx, ExprSet | ExprSize16 },
1437 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1438 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
1439 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1440 { ExprConstant[0] , 0x16, ExprUsed | ExprSize8 | ExprUnsignedHex },
1441 };
1442 0000000000000000: 66 f7 e8 imul %ax
1443 f7 / 5 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o
1444 Imul {%redx}, {%reax}, $Ev
1445 RegREDX OpSet OpImplicit
1446 RegREAX OpUse OpSet OpImplicit
1447 E_Operand OpUse
1448 NaClExpVector[6] = {
1449 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1450 { ExprRegister[0] , %dx, ExprSet | ExprSize16 },
1451 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1452 { ExprRegister[0] , %ax, ExprSet | ExprUsed | ExprSize16 },
1453 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1454 { ExprRegister[0] , %ax, ExprUsed | ExprSize16 },
1455 };
1456 0000000000000000: f6 ec imul %ah
1457 f6 / 5 386 OpcodeInModRm OpcodeUsesModRm OperandSize_b
1458 Imul {%ax}, {%al}, $Eb
1459 RegAX OpSet OpImplicit
1460 RegAL OpUse OpImplicit
1461 E_Operand OpUse
1462 NaClExpVector[6] = {
1463 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1464 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
1465 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1466 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
1467 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1468 { ExprRegister[0] , %ah, ExprUsed | ExprSize8 },
1469 };
1470 0000000000000000: 0f af 91 70 01 00 00 imul %edx, [%rcx+ 0x170]
1471 0f af 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
1472 Imul $Gv, $Ev
1473 G_Operand OpUse OpSet OperandZeroExtends_v
1474 E_Operand OpUse
1475 NaClExpVector[8] = {
1476 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1477 { ExprRegister[0] , %edx, ExprSet | ExprUsed | ExprSize32 },
1478 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1479 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1480 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
1481 { ExprRegister[0] , %unknown, 0 },
1482 { ExprConstant[0] , 1, ExprSize8 },
1483 { ExprConstant[0] , 0x170, ExprSize32 | ExprSignedHex },
1484 };
1485 0000000000000000: 0f af c1 imul %eax, %ecx
1486 0f af 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
1487 Imul $Gv, $Ev
1488 G_Operand OpUse OpSet OperandZeroExtends_v
1489 E_Operand OpUse
1490 NaClExpVector[4] = {
1491 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1492 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1493 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1494 { ExprRegister[0] , %ecx, ExprUsed | ExprSize32 },
1495 };
1496 0000000000000000: f6 fc idiv %ah
1497 f6 / 7 386 OpcodeInModRm OpcodeUsesModRm OperandSize_b
1498 Idiv {%ax}, {%al}, $Eb
1499 RegAX OpSet OpImplicit
1500 RegAL OpUse OpImplicit
1501 E_Operand OpUse
1502 NaClExpVector[6] = {
1503 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1504 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
1505 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1506 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
1507 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1508 { ExprRegister[0] , %ah, ExprUsed | ExprSize8 },
1509 };
1510 0000000000000000: f7 f9 idiv %ecx
1511 f7 / 7 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o
1512 Idiv {%redx}, {%reax}, $Ev
1513 RegREDX OpSet OpImplicit
1514 RegREAX OpUse OpSet OpImplicit
1515 E_Operand OpUse
1516 NaClExpVector[6] = {
1517 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1518 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
1519 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1520 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1521 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1522 { ExprRegister[0] , %ecx, ExprUsed | ExprSize32 },
1523 };
1524 0000000000000000: f7 be 70 01 00 00 idiv [%rsi+0x170]
1525 f7 / 7 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o
1526 Idiv {%redx}, {%reax}, $Ev
1527 RegREDX OpSet OpImplicit
1528 RegREAX OpUse OpSet OpImplicit
1529 E_Operand OpUse
1530 NaClExpVector[10] = {
1531 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1532 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
1533 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1534 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1535 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1536 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1537 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
1538 { ExprRegister[0] , %unknown, 0 },
1539 { ExprConstant[0] , 1, ExprSize8 },
1540 { ExprConstant[0] , 0x170, ExprSize32 | ExprSignedHex },
1541 };
1542 0000000000000000: 48 f7 f9 idiv %rcx
1543 f7 / 7 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o
1544 Idiv {%redx}, {%reax}, $Ev
1545 RegREDX OpSet OpImplicit
1546 RegREAX OpUse OpSet OpImplicit
1547 E_Operand OpUse
1548 NaClExpVector[6] = {
1549 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1550 { ExprRegister[0] , %rdx, ExprSet | ExprSize64 },
1551 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1552 { ExprRegister[0] , %rax, ExprSet | ExprUsed | ExprSize64 },
1553 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1554 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
1555 };
1556 0000000000000000: fc cld
1557 fc 386
1558 Cld
1559 NaClExpVector[0] = {
1560 };
1561 0000000000000000: f6 d8 neg %al
1562 f6 / 3 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b
1563 Neg $Eb
1564 E_Operand OpUse OpSet
1565 NaClExpVector[2] = {
1566 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1567 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
1568 };
1569 0000000000000000: f7 d9 neg %ecx
1570 f7 / 3 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
1571 Neg $Ev
1572 E_Operand OpUse OpSet OperandZeroExtends_v
1573 NaClExpVector[2] = {
1574 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1575 { ExprRegister[0] , %ecx, ExprSet | ExprUsed | ExprSize32 },
1576 };
1577 0000000000000000: 49 f7 de neg %r14
1578 f7 / 3 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
1579 Neg $Ev
1580 E_Operand OpUse OpSet OperandZeroExtends_v
1581 NaClExpVector[2] = {
1582 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1583 { ExprRegister[0] , %r14, ExprSet | ExprUsed | ExprSize64 },
1584 };
1585 0000000000000000: 48 f7 da neg %rdx
1586 f7 / 3 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
1587 Neg $Ev
1588 E_Operand OpUse OpSet OperandZeroExtends_v
1589 NaClExpVector[2] = {
1590 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1591 { ExprRegister[0] , %rdx, ExprSet | ExprUsed | ExprSize64 },
1592 };
1593 0000000000000000: f6 d1 not %cl
1594 f6 / 2 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b
1595 Not $Eb
1596 E_Operand OpUse OpSet
1597 NaClExpVector[2] = {
1598 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1599 { ExprRegister[0] , %cl, ExprSet | ExprUsed | ExprSize8 },
1600 };
1601 0000000000000000: f7 d1 not %ecx
1602 f7 / 2 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
1603 Not $Ev
1604 E_Operand OpUse OpSet OperandZeroExtends_v
1605 NaClExpVector[2] = {
1606 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1607 { ExprRegister[0] , %ecx, ExprSet | ExprUsed | ExprSize32 },
1608 };
1609 0000000000000000: 48 f7 d2 not %rdx
1610 f7 / 2 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
1611 Not $Ev
1612 E_Operand OpUse OpSet OperandZeroExtends_v
1613 NaClExpVector[2] = {
1614 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1615 { ExprRegister[0] , %rdx, ExprSet | ExprUsed | ExprSize64 },
1616 };
1617 0000000000000000: f6 e2 mul %dl
1618 f6 / 4 386 OpcodeInModRm OpcodeUsesModRm OperandSize_b
1619 Mul {%ax}, {%al}, $Eb
1620 RegAX OpSet OpImplicit
1621 RegAL OpUse OpImplicit
1622 E_Operand OpUse
1623 NaClExpVector[6] = {
1624 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1625 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
1626 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1627 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
1628 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1629 { ExprRegister[0] , %dl, ExprUsed | ExprSize8 },
1630 };
1631 0000000000000000: f7 e2 mul %edx
1632 f7 / 4 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o
1633 Mul {%redx}, {%reax}, $Ev
1634 RegREDX OpSet OpImplicit
1635 RegREAX OpUse OpSet OpImplicit
1636 E_Operand OpUse
1637 NaClExpVector[6] = {
1638 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1639 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
1640 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1641 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1642 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1643 { ExprRegister[0] , %edx, ExprUsed | ExprSize32 },
1644 };
1645 0000000000000000: 48 f7 e7 mul %rdi
1646 f7 / 4 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o
1647 Mul {%redx}, {%reax}, $Ev
1648 RegREDX OpSet OpImplicit
1649 RegREAX OpUse OpSet OpImplicit
1650 E_Operand OpUse
1651 NaClExpVector[6] = {
1652 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1653 { ExprRegister[0] , %rdx, ExprSet | ExprSize64 },
1654 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1655 { ExprRegister[0] , %rax, ExprSet | ExprUsed | ExprSize64 },
1656 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1657 { ExprRegister[0] , %rdi, ExprUsed | ExprSize64 },
1658 };
1659 0000000000000000: 41 f7 e6 mul %r14d
1660 f7 / 4 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o
1661 Mul {%redx}, {%reax}, $Ev
1662 RegREDX OpSet OpImplicit
1663 RegREAX OpUse OpSet OpImplicit
1664 E_Operand OpUse
1665 NaClExpVector[6] = {
1666 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1667 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
1668 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1669 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1670 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1671 { ExprRegister[0] , %r14d, ExprUsed | ExprSize32 },
1672 };
1673 0000000000000000: 48 f7 f1 div %rcx
1674 f7 / 6 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o
1675 Div {%redx}, {%reax}, $Ev
1676 RegREDX OpSet OpImplicit
1677 RegREAX OpUse OpSet OpImplicit
1678 E_Operand OpUse
1679 NaClExpVector[6] = {
1680 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1681 { ExprRegister[0] , %rdx, ExprSet | ExprSize64 },
1682 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1683 { ExprRegister[0] , %rax, ExprSet | ExprUsed | ExprSize64 },
1684 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1685 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
1686 };
1687 0000000000000000: 48 f7 71 38 div [%rcx+0x38]
1688 f7 / 6 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o
1689 Div {%redx}, {%reax}, $Ev
1690 RegREDX OpSet OpImplicit
1691 RegREAX OpUse OpSet OpImplicit
1692 E_Operand OpUse
1693 NaClExpVector[10] = {
1694 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1695 { ExprRegister[0] , %rdx, ExprSet | ExprSize64 },
1696 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1697 { ExprRegister[0] , %rax, ExprSet | ExprUsed | ExprSize64 },
1698 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1699 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1700 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
1701 { ExprRegister[0] , %unknown, 0 },
1702 { ExprConstant[0] , 1, ExprSize8 },
1703 { ExprConstant[0] , 0x38, ExprSize8 | ExprSignedHex },
1704 };
1705 0000000000000000: f7 35 37 af 57 00 div [%rip+0x57af3 7]
1706 f7 / 6 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o
1707 Div {%redx}, {%reax}, $Ev
1708 RegREDX OpSet OpImplicit
1709 RegREAX OpUse OpSet OpImplicit
1710 E_Operand OpUse
1711 NaClExpVector[10] = {
1712 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1713 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
1714 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
1715 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1716 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1717 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1718 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
1719 { ExprRegister[0] , %unknown, 0 },
1720 { ExprConstant[0] , 1, ExprSize8 },
1721 { ExprConstant[0] , 0x57af37, ExprSize32 | ExprSignedHex },
1722 };
1723 0000000000000000: f2 0f 10 05 b5 dc 15 00 movsd %xmm0, [%ri p+0x15dcb5]
1724 f2 0f 10 SSE2 OpcodeUsesModRm OpcodeAllowsRepne
1725 Movsd $Vsd, $Wsd
1726 Xmm_G_Operand OpSet
1727 Xmm_E_Operand OpUse
1728 NaClExpVector[8] = {
1729 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1730 { ExprRegister[0] , %xmm0, ExprSet },
1731 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1732 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1733 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
1734 { ExprRegister[0] , %unknown, 0 },
1735 { ExprConstant[0] , 1, ExprSize8 },
1736 { ExprConstant[0] , 0x15dcb5, ExprSize32 | ExprSignedHex },
1737 };
1738 0000000000000000: f2 0f 11 54 24 10 movsd [%rsp+0x10] , %xmm2
1739 f2 0f 11 SSE2 OpcodeUsesModRm OpcodeAllowsRepne
1740 Movsd $Wsd, $Vsd
1741 Xmm_E_Operand OpSet
1742 Xmm_G_Operand OpUse
1743 NaClExpVector[8] = {
1744 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1745 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
1746 { ExprRegister[0] , %rsp, ExprUsed | ExprSize64 },
1747 { ExprRegister[0] , %unknown, 0 },
1748 { ExprConstant[0] , 1, ExprSize8 },
1749 { ExprConstant[0] , 0x10, ExprSize8 | ExprSignedHex },
1750 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1751 { ExprRegister[0] , %xmm2, ExprUsed },
1752 };
1753 0000000000000000: f3 0f 10 02 movss %xmm0, [%rd x]
1754 f3 0f 10 SSE OpcodeUsesModRm OpcodeAllowsRep
1755 Movss $Vss, $Wss
1756 Xmm_G_Operand OpSet
1757 Xmm_E_Operand OpUse
1758 NaClExpVector[8] = {
1759 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1760 { ExprRegister[0] , %xmm0, ExprSet },
1761 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1762 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1763 { ExprRegister[0] , %rdx, ExprUsed | ExprSize64 },
1764 { ExprRegister[0] , %unknown, 0 },
1765 { ExprConstant[0] , 1, ExprSize8 },
1766 { ExprConstant[0] , 0, ExprSize8 },
1767 };
1768 0000000000000000: f3 0f 11 44 24 0c movss [%rsp+0xc], %xmm0
1769 f3 0f 11 SSE OpcodeUsesModRm OpcodeAllowsRep
1770 Movss $Wss, $Vss
1771 Xmm_E_Operand OpSet
1772 Xmm_G_Operand OpUse
1773 NaClExpVector[8] = {
1774 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1775 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
1776 { ExprRegister[0] , %rsp, ExprUsed | ExprSize64 },
1777 { ExprRegister[0] , %unknown, 0 },
1778 { ExprConstant[0] , 1, ExprSize8 },
1779 { ExprConstant[0] , 0xc, ExprSize8 | ExprSignedHex },
1780 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1781 { ExprRegister[0] , %xmm0, ExprUsed },
1782 };
1783 0000000000000000: f3 0f 10 4c 24 1c movss %xmm1, [%rs p+0x1c]
1784 f3 0f 10 SSE OpcodeUsesModRm OpcodeAllowsRep
1785 Movss $Vss, $Wss
1786 Xmm_G_Operand OpSet
1787 Xmm_E_Operand OpUse
1788 NaClExpVector[8] = {
1789 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1790 { ExprRegister[0] , %xmm1, ExprSet },
1791 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1792 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1793 { ExprRegister[0] , %rsp, ExprUsed | ExprSize64 },
1794 { ExprRegister[0] , %unknown, 0 },
1795 { ExprConstant[0] , 1, ExprSize8 },
1796 { ExprConstant[0] , 0x1c, ExprSize8 | ExprSignedHex },
1797 };
1798 0000000000000000: f3 0f 11 44 24 0c movss [%rsp+0xc], %xmm0
1799 f3 0f 11 SSE OpcodeUsesModRm OpcodeAllowsRep
1800 Movss $Wss, $Vss
1801 Xmm_E_Operand OpSet
1802 Xmm_G_Operand OpUse
1803 NaClExpVector[8] = {
1804 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1805 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
1806 { ExprRegister[0] , %rsp, ExprUsed | ExprSize64 },
1807 { ExprRegister[0] , %unknown, 0 },
1808 { ExprConstant[0] , 1, ExprSize8 },
1809 { ExprConstant[0] , 0xc, ExprSize8 | ExprSignedHex },
1810 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1811 { ExprRegister[0] , %xmm0, ExprUsed },
1812 };
1813 0000000000000000: f2 0f 5f cf maxsd %xmm1, %xmm 7
1814 f2 0f 5f SSE2 OpcodeUsesModRm OpcodeAllowsRepne
1815 Maxsd $Vsd, $Wsd
1816 Xmm_G_Operand OpUse OpSet
1817 Xmm_E_Operand OpUse
1818 NaClExpVector[4] = {
1819 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1820 { ExprRegister[0] , %xmm1, ExprSet | ExprUsed },
1821 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1822 { ExprRegister[0] , %xmm7, ExprUsed },
1823 };
1824 0000000000000000: 0f c8 bswap %eax
1825 0f c8 - r0 386 OpcodePlusR OperandSize_v
1826 Bswap $r8vd
1827 G_OpcodeBase OpUse OpSet
1828 NaClExpVector[2] = {
1829 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1830 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
1831 };
1832 0000000000000000: 48 0f c8 bswap %rax
1833 0f c8 - r0 386 OpcodePlusR OperandSize_o
1834 Bswap $r8vq
1835 G_OpcodeBase OpUse OpSet
1836 NaClExpVector[2] = {
1837 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1838 { ExprRegister[0] , %rax, ExprSet | ExprUsed | ExprSize64 },
1839 };
1840 0000000000000000: 49 0f cd bswap %r13
1841 0f cd - r5 386 OpcodePlusR OperandSize_o
1842 Bswap $r8vq
1843 G_OpcodeBase OpUse OpSet
1844 NaClExpVector[2] = {
1845 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1846 { ExprRegister[0] , %r13, ExprSet | ExprUsed | ExprSize64 },
1847 };
1848 0000000000000000: 0f 6e 11 movd %mmx2, [%rcx ]
1849 0f 6e MMX OpcodeUsesModRm SizeIgnoresData16 OperandSize_ v
1850 Movd $Pq, $Ed/q/d
1851 Mmx_G_Operand OpSet OperandZeroExtends_v
1852 E_Operand OpUse
1853 NaClExpVector[8] = {
1854 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1855 { ExprRegister[0] , %mmx2, ExprSet },
1856 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1857 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1858 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
1859 { ExprRegister[0] , %unknown, 0 },
1860 { ExprConstant[0] , 1, ExprSize8 },
1861 { ExprConstant[0] , 0, ExprSize8 },
1862 };
1863 0000000000000000: 49 0f 6e 11 movq %mmx2, [%r9]
1864 0f 6e MMX OpcodeUsesModRm SizeIgnoresData16 OperandSize_ o
1865 Movq $Pq, $Ed/q/q
1866 Mmx_G_Operand OpSet
1867 E_Operand OpUse
1868 NaClExpVector[8] = {
1869 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1870 { ExprRegister[0] , %mmx2, ExprSet },
1871 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1872 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1873 { ExprRegister[0] , %r9, ExprUsed | ExprSize64 },
1874 { ExprRegister[0] , %unknown, 0 },
1875 { ExprConstant[0] , 1, ExprSize8 },
1876 { ExprConstant[0] , 0, ExprSize8 },
1877 };
1878 0000000000000000: 66 0f 6e 11 movd %xmm2, [%rcx ]
1879 66 0f 6e SSE2 OpcodeUsesModRm OpcodeAllowsData16 SizeIgnore sData16 OperandSize_v
1880 Movd $Vdq, $Ed/q/d
1881 Xmm_G_Operand OpSet OperandZeroExtends_v
1882 E_Operand OpUse
1883 NaClExpVector[8] = {
1884 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1885 { ExprRegister[0] , %xmm2, ExprSet },
1886 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1887 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1888 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
1889 { ExprRegister[0] , %unknown, 0 },
1890 { ExprConstant[0] , 1, ExprSize8 },
1891 { ExprConstant[0] , 0, ExprSize8 },
1892 };
1893 0000000000000000: 0f 7e 0e movd [%rsi], %mmx 1
1894 0f 7e MMX OpcodeUsesModRm SizeIgnoresData16 OperandSize_ v
1895 Movd $Ed/q/d, $Pd/q/d
1896 E_Operand OpSet OperandZeroExtends_v
1897 Mmx_G_Operand OpUse
1898 NaClExpVector[8] = {
1899 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1900 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
1901 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
1902 { ExprRegister[0] , %unknown, 0 },
1903 { ExprConstant[0] , 1, ExprSize8 },
1904 { ExprConstant[0] , 0, ExprSize8 },
1905 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1906 { ExprRegister[0] , %mmx1, ExprUsed },
1907 };
1908 0000000000000000: 49 0f 7e 0e movq [%r14], %mmx 1
1909 0f 7e MMX OpcodeUsesModRm SizeIgnoresData16 OperandSize_ o
1910 Movq $Ed/q/q, $Pd/q/q
1911 E_Operand OpSet
1912 Mmx_G_Operand OpUse
1913 NaClExpVector[8] = {
1914 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1915 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
1916 { ExprRegister[0] , %r14, ExprUsed | ExprSize64 },
1917 { ExprRegister[0] , %unknown, 0 },
1918 { ExprConstant[0] , 1, ExprSize8 },
1919 { ExprConstant[0] , 0, ExprSize8 },
1920 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1921 { ExprRegister[0] , %mmx1, ExprUsed },
1922 };
1923 0000000000000000: 0f 77 emms
1924 0f 77 MMX
1925 Emms
1926 NaClExpVector[0] = {
1927 };
1928 0000000000000000: f2 0f c2 c7 01 cmpsd_xmm %xmm0, %xmm7, 0x1
1929 f2 0f c2 SSE2 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllows Repne
1930 Cmpsd_xmm $Vsd, $Wsd, $Ib
1931 Xmm_G_Operand OpUse OpSet
1932 Xmm_E_Operand OpUse
1933 I_Operand OpUse
1934 NaClExpVector[6] = {
1935 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1936 { ExprRegister[0] , %xmm0, ExprSet | ExprUsed },
1937 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1938 { ExprRegister[0] , %xmm7, ExprUsed },
1939 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1940 { ExprConstant[0] , 0x1, ExprUsed | ExprSize8 | ExprUnsignedHex },
1941 };
1942 0000000000000000: f2 0f c2 0d 67 87 10 00 05 cmpsd_xmm %xmm1, [%rip+0x108767], 0x5
1943 f2 0f c2 SSE2 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllows Repne
1944 Cmpsd_xmm $Vsd, $Wsd, $Ib
1945 Xmm_G_Operand OpUse OpSet
1946 Xmm_E_Operand OpUse
1947 I_Operand OpUse
1948 NaClExpVector[10] = {
1949 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1950 { ExprRegister[0] , %xmm1, ExprSet | ExprUsed },
1951 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1952 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1953 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
1954 { ExprRegister[0] , %unknown, 0 },
1955 { ExprConstant[0] , 1, ExprSize8 },
1956 { ExprConstant[0] , 0x108767, ExprSize32 | ExprSignedHex },
1957 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1958 { ExprConstant[0] , 0x5, ExprUsed | ExprSize8 | ExprUnsignedHex },
1959 };
1960 0000000000000000: f3 0f c2 c7 01 cmpss %xmm0, %xmm 7, 0x1
1961 f3 0f c2 SSE OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsR ep
1962 Cmpss $Vss, $Wss, $Ib
1963 Xmm_G_Operand OpUse OpSet
1964 Xmm_E_Operand OpUse
1965 I_Operand OpUse
1966 NaClExpVector[6] = {
1967 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1968 { ExprRegister[0] , %xmm0, ExprSet | ExprUsed },
1969 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1970 { ExprRegister[0] , %xmm7, ExprUsed },
1971 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1972 { ExprConstant[0] , 0x1, ExprUsed | ExprSize8 | ExprUnsignedHex },
1973 };
1974 0000000000000000: f3 0f c2 0d 67 87 10 00 05 cmpss %xmm1, [%ri p+0x108767], 0x5
1975 f3 0f c2 SSE OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsR ep
1976 Cmpss $Vss, $Wss, $Ib
1977 Xmm_G_Operand OpUse OpSet
1978 Xmm_E_Operand OpUse
1979 I_Operand OpUse
1980 NaClExpVector[10] = {
1981 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1982 { ExprRegister[0] , %xmm1, ExprSet | ExprUsed },
1983 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
1984 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
1985 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
1986 { ExprRegister[0] , %unknown, 0 },
1987 { ExprConstant[0] , 1, ExprSize8 },
1988 { ExprConstant[0] , 0x108767, ExprSize32 | ExprSignedHex },
1989 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
1990 { ExprConstant[0] , 0x5, ExprUsed | ExprSize8 | ExprUnsignedHex },
1991 };
1992 0000000000000000: 0f 6f 05 ba 87 0f 00 movq %mmx0, [%rip +0xf87ba]
1993 0f 6f MMX OpcodeUsesModRm
1994 Movq $Pq, $Qq
1995 Mmx_G_Operand OpSet
1996 Mmx_E_Operand OpUse
1997 NaClExpVector[8] = {
1998 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
1999 { ExprRegister[0] , %mmx0, ExprSet },
2000 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2001 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2002 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
2003 { ExprRegister[0] , %unknown, 0 },
2004 { ExprConstant[0] , 1, ExprSize8 },
2005 { ExprConstant[0] , 0xf87ba, ExprSize32 | ExprSignedHex },
2006 };
2007 0000000000000000: 0f 6f c8 movq %mmx1, %mmx0
2008 0f 6f MMX OpcodeUsesModRm
2009 Movq $Pq, $Qq
2010 Mmx_G_Operand OpSet
2011 Mmx_E_Operand OpUse
2012 NaClExpVector[4] = {
2013 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2014 { ExprRegister[0] , %mmx1, ExprSet },
2015 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2016 { ExprRegister[0] , %mmx0, ExprUsed },
2017 };
2018 0000000000000000: 0f 7f 0e movq [%rsi], %mmx 1
2019 0f 7f MMX OpcodeUsesModRm
2020 Movq $Qq, $Pq
2021 Mmx_E_Operand OpSet
2022 Mmx_G_Operand OpUse
2023 NaClExpVector[8] = {
2024 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2025 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
2026 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
2027 { ExprRegister[0] , %unknown, 0 },
2028 { ExprConstant[0] , 1, ExprSize8 },
2029 { ExprConstant[0] , 0, ExprSize8 },
2030 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2031 { ExprRegister[0] , %mmx1, ExprUsed },
2032 };
2033 0000000000000000: 0f d1 0c 25 08 00 00 00 psrlw %mmx1, [0x8 ]
2034 0f d1 MMX OpcodeUsesModRm
2035 Psrlw $Pq, $Qq
2036 Mmx_G_Operand OpUse OpSet
2037 Mmx_E_Operand OpUse
2038 NaClExpVector[8] = {
2039 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2040 { ExprRegister[0] , %mmx1, ExprSet | ExprUsed },
2041 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2042 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2043 { ExprRegister[0] , %unknown, 0 },
2044 { ExprRegister[0] , %unknown, 0 },
2045 { ExprConstant[0] , 1, ExprSize8 },
2046 { ExprConstant[0] , 0x8, ExprSize32 | ExprSignedHex },
2047 };
2048 0000000000000000: 0f 71 d1 08 psrlw %mmx1, 0x8
2049 0f 71 / 2 MMX OpcodeInModRm ModRmModIs0x3 OpcodeUsesModRm Op codeHasImmed_b
2050 Psrlw $PRq, $Ib
2051 Mmx_E_Operand OpUse OpSet
2052 I_Operand OpUse
2053 NaClExpVector[4] = {
2054 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2055 { ExprRegister[0] , %mmx1, ExprSet | ExprUsed },
2056 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2057 { ExprConstant[0] , 0x8, ExprUsed | ExprSize8 | ExprUnsignedHex },
2058 };
2059 0000000000000000: 0f 6e e8 movd %mmx5, %eax
2060 0f 6e MMX OpcodeUsesModRm SizeIgnoresData16 OperandSize_ v
2061 Movd $Pq, $Ed/q/d
2062 Mmx_G_Operand OpSet OperandZeroExtends_v
2063 E_Operand OpUse
2064 NaClExpVector[4] = {
2065 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2066 { ExprRegister[0] , %mmx5, ExprSet },
2067 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2068 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
2069 };
2070 0000000000000000: f3 0f 6f 05 f9 77 0f 00 movdqu %xmm0, [%r ip+0xf77f9]
2071 f3 0f 6f SSE2 OpcodeUsesModRm OpcodeAllowsRep
2072 Movdqu $Vdq, $Wdq
2073 Xmm_G_Operand OpSet
2074 Xmm_E_Operand OpUse
2075 NaClExpVector[8] = {
2076 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2077 { ExprRegister[0] , %xmm0, ExprSet },
2078 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2079 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2080 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
2081 { ExprRegister[0] , %unknown, 0 },
2082 { ExprConstant[0] , 1, ExprSize8 },
2083 { ExprConstant[0] , 0xf77f9, ExprSize32 | ExprSignedHex },
2084 };
2085 0000000000000000: f3 0f 6f 11 movdqu %xmm2, [%r cx]
2086 f3 0f 6f SSE2 OpcodeUsesModRm OpcodeAllowsRep
2087 Movdqu $Vdq, $Wdq
2088 Xmm_G_Operand OpSet
2089 Xmm_E_Operand OpUse
2090 NaClExpVector[8] = {
2091 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2092 { ExprRegister[0] , %xmm2, ExprSet },
2093 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2094 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2095 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
2096 { ExprRegister[0] , %unknown, 0 },
2097 { ExprConstant[0] , 1, ExprSize8 },
2098 { ExprConstant[0] , 0, ExprSize8 },
2099 };
2100 0000000000000000: f3 0f 7f 0e movdqu [%rsi], %x mm1
2101 f3 0f 7f SSE2 OpcodeUsesModRm OpcodeAllowsRep
2102 Movdqu $Wdq, $Vdq
2103 Xmm_E_Operand OpSet
2104 Xmm_G_Operand OpUse
2105 NaClExpVector[8] = {
2106 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2107 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
2108 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
2109 { ExprRegister[0] , %unknown, 0 },
2110 { ExprConstant[0] , 1, ExprSize8 },
2111 { ExprConstant[0] , 0, ExprSize8 },
2112 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2113 { ExprRegister[0] , %xmm1, ExprUsed },
2114 };
2115 0000000000000000: 0f e7 0e movntq [%rsi], %m mx1
2116 0f e7 MMX ModRmModIsnt0x3 OpcodeUsesModRm
2117 Movntq $Mq, $Pq
2118 Mo_Operand OpSet
2119 Mmx_G_Operand OpUse
2120 NaClExpVector[8] = {
2121 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2122 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
2123 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
2124 { ExprRegister[0] , %unknown, 0 },
2125 { ExprConstant[0] , 1, ExprSize8 },
2126 { ExprConstant[0] , 0, ExprSize8 },
2127 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2128 { ExprRegister[0] , %mmx1, ExprUsed },
2129 };
2130 0000000000000000: 66 0f 29 0c 24 movapd [%rsp], %x mm1
2131 66 0f 29 SSE2 OpcodeUsesModRm OpcodeAllowsData16 SizeIgnore sData16
2132 Movapd $Wpd, $Vpd
2133 Xmm_E_Operand OpSet
2134 Xmm_G_Operand OpUse
2135 NaClExpVector[8] = {
2136 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2137 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
2138 { ExprRegister[0] , %rsp, ExprUsed | ExprSize64 },
2139 { ExprRegister[0] , %unknown, 0 },
2140 { ExprConstant[0] , 1, ExprSize8 },
2141 { ExprConstant[0] , 0, ExprSize8 },
2142 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2143 { ExprRegister[0] , %xmm1, ExprUsed },
2144 };
2145 0000000000000000: f3 0f 51 d0 sqrtss %xmm2, %xm m0
2146 f3 0f 51 SSE OpcodeUsesModRm OpcodeAllowsRep
2147 Sqrtss $Vps, $Wps
2148 Xmm_G_Operand OpSet
2149 Xmm_E_Operand OpUse
2150 NaClExpVector[4] = {
2151 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2152 { ExprRegister[0] , %xmm2, ExprSet },
2153 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2154 { ExprRegister[0] , %xmm0, ExprUsed },
2155 };
2156 0000000000000000: 48 ff c0 inc %rax
2157 ff / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
2158 Inc $Ev
2159 E_Operand OpUse OpSet OperandZeroExtends_v
2160 NaClExpVector[2] = {
2161 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2162 { ExprRegister[0] , %rax, ExprSet | ExprUsed | ExprSize64 },
2163 };
2164 0000000000000000: ff 05 a4 76 39 00 inc [%rip+0x3976a 4]
2165 ff / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
2166 Inc $Ev
2167 E_Operand OpUse OpSet OperandZeroExtends_v
2168 NaClExpVector[6] = {
2169 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2170 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2171 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
2172 { ExprRegister[0] , %unknown, 0 },
2173 { ExprConstant[0] , 1, ExprSize8 },
2174 { ExprConstant[0] , 0x3976a4, ExprSize32 | ExprSignedHex },
2175 };
2176 0000000000000000: ff c0 inc %eax
2177 ff / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
2178 Inc $Ev
2179 E_Operand OpUse OpSet OperandZeroExtends_v
2180 NaClExpVector[2] = {
2181 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2182 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
2183 };
2184 0000000000000000: 41 ff c5 inc %r13d
2185 ff / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
2186 Inc $Ev
2187 E_Operand OpUse OpSet OperandZeroExtends_v
2188 NaClExpVector[2] = {
2189 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2190 { ExprRegister[0] , %r13d, ExprSet | ExprUsed | ExprSize32 },
2191 };
2192 0000000000000000: fe c0 inc %al
2193 fe / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b
2194 Inc $Eb
2195 E_Operand OpUse OpSet
2196 NaClExpVector[2] = {
2197 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2198 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
2199 };
2200 0000000000000000: fe c4 inc %ah
2201 fe / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b
2202 Inc $Eb
2203 E_Operand OpUse OpSet
2204 NaClExpVector[2] = {
2205 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2206 { ExprRegister[0] , %ah, ExprSet | ExprUsed | ExprSize8 },
2207 };
2208 0000000000000000: 41 fe c0 inc %r8b
2209 fe / 0 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b
2210 Inc $Eb
2211 E_Operand OpUse OpSet
2212 NaClExpVector[2] = {
2213 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2214 { ExprRegister[0] , %r8b, ExprSet | ExprUsed | ExprSize8 },
2215 };
2216 0000000000000000: ff ca dec %edx
2217 ff / 1 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
2218 Dec $Ev
2219 E_Operand OpUse OpSet OperandZeroExtends_v
2220 NaClExpVector[2] = {
2221 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2222 { ExprRegister[0] , %edx, ExprSet | ExprUsed | ExprSize32 },
2223 };
2224 0000000000000000: ff 0d 8f 76 39 00 dec [%rip+0x39768 f]
2225 ff / 1 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
2226 Dec $Ev
2227 E_Operand OpUse OpSet OperandZeroExtends_v
2228 NaClExpVector[6] = {
2229 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2230 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2231 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
2232 { ExprRegister[0] , %unknown, 0 },
2233 { ExprConstant[0] , 1, ExprSize8 },
2234 { ExprConstant[0] , 0x39768f, ExprSize32 | ExprSignedHex },
2235 };
2236 0000000000000000: 48 ff c8 dec %rax
2237 ff / 1 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
2238 Dec $Ev
2239 E_Operand OpUse OpSet OperandZeroExtends_v
2240 NaClExpVector[2] = {
2241 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2242 { ExprRegister[0] , %rax, ExprSet | ExprUsed | ExprSize64 },
2243 };
2244 0000000000000000: 49 ff cc dec %r12
2245 ff / 1 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O pcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
2246 Dec $Ev
2247 E_Operand OpUse OpSet OperandZeroExtends_v
2248 NaClExpVector[2] = {
2249 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2250 { ExprRegister[0] , %r12, ExprSet | ExprUsed | ExprSize64 },
2251 };
2252 0000000000000000: fe c8 dec %al
2253 fe / 1 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b
2254 Dec $Eb
2255 E_Operand OpUse OpSet
2256 NaClExpVector[2] = {
2257 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2258 { ExprRegister[0] , %al, ExprSet | ExprUsed | ExprSize8 },
2259 };
2260 0000000000000000: fe cc dec %ah
2261 fe / 1 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b
2262 Dec $Eb
2263 E_Operand OpUse OpSet
2264 NaClExpVector[2] = {
2265 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2266 { ExprRegister[0] , %ah, ExprSet | ExprUsed | ExprSize8 },
2267 };
2268 0000000000000000: 41 fe c8 dec %r8b
2269 fe / 1 386 OpcodeInModRm OpcodeUsesModRm OpcodeLockable O perandSize_b
2270 Dec $Eb
2271 E_Operand OpUse OpSet
2272 NaClExpVector[2] = {
2273 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2274 { ExprRegister[0] , %r8b, ExprSet | ExprUsed | ExprSize8 },
2275 };
2276 0000000000000000: f0 0f b1 35 21 c6 31 00 cmpxchg [%rip+0x3 1c621], %esi
2277 0f b1 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
2278 Cmpxchg {$rAXv}, $Ev, $Gv
2279 RegREAX OpUse OpSet OpImplicit
2280 E_Operand OpUse OpSet
2281 G_Operand OpUse OpSet
2282 NaClExpVector[10] = {
2283 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
2284 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
2285 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2286 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2287 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
2288 { ExprRegister[0] , %unknown, 0 },
2289 { ExprConstant[0] , 1, ExprSize8 },
2290 { ExprConstant[0] , 0x31c621, ExprSize32 | ExprSignedHex },
2291 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2292 { ExprRegister[0] , %esi, ExprSet | ExprUsed | ExprSize32 },
2293 };
2294 0000000000000000: 0f b1 35 12 c6 31 00 cmpxchg [%rip+0x3 1c612], %esi
2295 0f b1 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
2296 Cmpxchg {$rAXv}, $Ev, $Gv
2297 RegREAX OpUse OpSet OpImplicit
2298 E_Operand OpUse OpSet
2299 G_Operand OpUse OpSet
2300 NaClExpVector[10] = {
2301 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
2302 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
2303 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2304 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2305 { ExprRegister[0] , %rip, ExprUsed | ExprSize64 },
2306 { ExprRegister[0] , %unknown, 0 },
2307 { ExprConstant[0] , 1, ExprSize8 },
2308 { ExprConstant[0] , 0x31c612, ExprSize32 | ExprSignedHex },
2309 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2310 { ExprRegister[0] , %esi, ExprSet | ExprUsed | ExprSize32 },
2311 };
2312 0000000000000000: f0 41 0f b1 30 cmpxchg [%r8], %e si
2313 0f b1 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
2314 Cmpxchg {$rAXv}, $Ev, $Gv
2315 RegREAX OpUse OpSet OpImplicit
2316 E_Operand OpUse OpSet
2317 G_Operand OpUse OpSet
2318 NaClExpVector[10] = {
2319 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
2320 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
2321 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2322 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2323 { ExprRegister[0] , %r8, ExprUsed | ExprSize64 },
2324 { ExprRegister[0] , %unknown, 0 },
2325 { ExprConstant[0] , 1, ExprSize8 },
2326 { ExprConstant[0] , 0, ExprSize8 },
2327 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2328 { ExprRegister[0] , %esi, ExprSet | ExprUsed | ExprSize32 },
2329 };
2330 0000000000000000: f0 0f c1 02 xadd [%rdx], %eax
2331 0f c1 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
2332 Xadd $Ev, $Gv
2333 E_Operand OpUse OpSet OperandZeroExtends_v
2334 G_Operand OpUse OpSet OperandZeroExtends_v
2335 NaClExpVector[8] = {
2336 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2337 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2338 { ExprRegister[0] , %rdx, ExprUsed | ExprSize64 },
2339 { ExprRegister[0] , %unknown, 0 },
2340 { ExprConstant[0] , 1, ExprSize8 },
2341 { ExprConstant[0] , 0, ExprSize8 },
2342 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2343 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
2344 };
2345 0000000000000000: f0 0f c1 43 18 xadd [%rbx+0x18], %eax
2346 0f c1 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
2347 Xadd $Ev, $Gv
2348 E_Operand OpUse OpSet OperandZeroExtends_v
2349 G_Operand OpUse OpSet OperandZeroExtends_v
2350 NaClExpVector[8] = {
2351 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2352 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2353 { ExprRegister[0] , %rbx, ExprUsed | ExprSize64 },
2354 { ExprRegister[0] , %unknown, 0 },
2355 { ExprConstant[0] , 1, ExprSize8 },
2356 { ExprConstant[0] , 0x18, ExprSize8 | ExprSignedHex },
2357 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2358 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
2359 };
2360 0000000000000000: f0 41 0f c1 00 xadd [%r8], %eax
2361 0f c1 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o
2362 Xadd $Ev, $Gv
2363 E_Operand OpUse OpSet OperandZeroExtends_v
2364 G_Operand OpUse OpSet OperandZeroExtends_v
2365 NaClExpVector[8] = {
2366 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2367 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2368 { ExprRegister[0] , %r8, ExprUsed | ExprSize64 },
2369 { ExprRegister[0] , %unknown, 0 },
2370 { ExprConstant[0] , 1, ExprSize8 },
2371 { ExprConstant[0] , 0, ExprSize8 },
2372 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2373 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
2374 };
2375 0000000000000000: 0f 05 syscall
2376 0f 05 SYSCALL NaClIllegal
2377 Syscall {%rip}, {%rcx}
2378 RegRIP OpUse OpSet OpImplicit
2379 RegRCX OpSet OpImplicit
2380 NaClExpVector[4] = {
2381 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
2382 { ExprRegister[0] , %rip, ExprSet | ExprUsed | ExprSize64 },
2383 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
2384 { ExprRegister[0] , %rcx, ExprSet | ExprSize64 },
2385 };
2386 0000000000000000: e4 08 in %al, 0x8
2387 e4 386 OpcodeHasImmed_b NaClIllegal
2388 In %al, $Ib
2389 RegAL OpSet
2390 I_Operand OpUse
2391 NaClExpVector[4] = {
2392 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2393 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
2394 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2395 { ExprConstant[0] , 0x8, ExprUsed | ExprSize8 | ExprUnsignedHex },
2396 };
2397 0000000000000000: 66 e5 08 in %ax, 0x8
2398 e5 386 OpcodeHasImmed_b OpcodeAllowsData16 OperandSiz e_w OperandSize_v OperandSize_o NaClIllegal
2399 In $rAXv, $Ib
2400 RegREAX OpSet
2401 I_Operand OpUse
2402 NaClExpVector[4] = {
2403 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2404 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
2405 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2406 { ExprConstant[0] , 0x8, ExprUsed | ExprSize8 | ExprUnsignedHex },
2407 };
2408 0000000000000000: e5 08 in %eax, 0x8
2409 e5 386 OpcodeHasImmed_b OpcodeAllowsData16 OperandSiz e_w OperandSize_v OperandSize_o NaClIllegal
2410 In $rAXv, $Ib
2411 RegREAX OpSet
2412 I_Operand OpUse
2413 NaClExpVector[4] = {
2414 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2415 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
2416 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2417 { ExprConstant[0] , 0x8, ExprUsed | ExprSize8 | ExprUnsignedHex },
2418 };
2419 0000000000000000: ec in %al, %dx
2420 ec 386 NaClIllegal
2421 In %al, %dx
2422 RegAL OpSet
2423 RegDX OpUse
2424 NaClExpVector[4] = {
2425 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2426 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
2427 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2428 { ExprRegister[0] , %dx, ExprUsed | ExprSize16 },
2429 };
2430 0000000000000000: 66 ed in %ax, %dx
2431 ed 386 OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o NaClIllegal
2432 In $rAXv, %dx
2433 RegREAX OpSet
2434 RegDX OpUse
2435 NaClExpVector[4] = {
2436 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2437 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
2438 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2439 { ExprRegister[0] , %dx, ExprUsed | ExprSize16 },
2440 };
2441 0000000000000000: ed in %eax, %dx
2442 ed 386 OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o NaClIllegal
2443 In $rAXv, %dx
2444 RegREAX OpSet
2445 RegDX OpUse
2446 NaClExpVector[4] = {
2447 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2448 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
2449 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2450 { ExprRegister[0] , %dx, ExprUsed | ExprSize16 },
2451 };
2452 0000000000000000: 55 push %rbp
2453 55 - r5 386 OpcodePlusR OpcodeAllowsData16 OperandSize_w O perandSize_v OperandSize_o OperandSizeDefaultIs64
2454 Push {%rsp}, $r8v
2455 RegRSP OpUse OpSet OpImplicit
2456 G_OpcodeBase OpUse
2457 NaClExpVector[4] = {
2458 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
2459 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
2460 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2461 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
2462 };
2463 0000000000000000: 0f 18 86 00 03 00 00 prefetchnta [%rsi +0x300]
2464 0f 18 / 0 MMX OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm
2465 Prefetchnta $Mb
2466 Mb_Operand
2467 NaClExpVector[6] = {
2468 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2469 { ExprMemOffset[4] , 0, ExprSize64 },
2470 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
2471 { ExprRegister[0] , %unknown, 0 },
2472 { ExprConstant[0] , 1, ExprSize8 },
2473 { ExprConstant[0] , 0x300, ExprSize32 | ExprSignedHex },
2474 };
2475 0000000000000000: 48 0f c3 07 movnti [%rdi], %r ax
2476 0f c3 SSE2 ModRmModIsnt0x3 OpcodeUsesModRm SizeIgnoresDa ta16 OperandSize_v OperandSize_o
2477 Movnti $Md/q, $Gd/q
2478 M_Operand OpSet
2479 G_Operand OpUse
2480 NaClExpVector[8] = {
2481 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2482 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
2483 { ExprRegister[0] , %rdi, ExprUsed | ExprSize64 },
2484 { ExprRegister[0] , %unknown, 0 },
2485 { ExprConstant[0] , 1, ExprSize8 },
2486 { ExprConstant[0] , 0, ExprSize8 },
2487 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2488 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2489 };
2490 0000000000000000: 0f ae f8 sfence
2491 0f ae / 7 / 0 SFENCE_CLFLUSH OpcodeInModRm OpcodeInModRmRm ModRm ModIs0x3 OpcodeUsesModRm
2492 Sfence
2493 NaClExpVector[0] = {
2494 };
2495 0000000000000000: 41 0f a3 c0 bt %r8d, %eax
2496 0f a3 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o NaClIllegal
2497 Bt $Ev, $Gv
2498 E_Operand OpUse
2499 G_Operand OpUse
2500 NaClExpVector[4] = {
2501 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2502 { ExprRegister[0] , %r8d, ExprUsed | ExprSize32 },
2503 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2504 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
2505 };
2506 0000000000000000: 41 db 2c 07 fld %st0, [%r15+% rax*1]
2507 db / 5 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm
2508 Fld %st0, $Mf
2509 RegST0 OpSet
2510 M_Operand OpUse
2511 NaClExpVector[8] = {
2512 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2513 { ExprRegister[0] , %st0, ExprSet },
2514 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2515 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2516 { ExprRegister[0] , %r15, ExprUsed | ExprSize64 },
2517 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2518 { ExprConstant[0] , 1, ExprSize8 },
2519 { ExprConstant[0] , 0, ExprSize8 },
2520 };
2521 0000000000000000: dd 04 24 fld %st0, [%rsp]
2522 dd / 0 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm
2523 Fld %st0, $Mq
2524 RegST0 OpSet
2525 Mo_Operand OpUse
2526 NaClExpVector[8] = {
2527 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2528 { ExprRegister[0] , %st0, ExprSet },
2529 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2530 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2531 { ExprRegister[0] , %rsp, ExprUsed | ExprSize64 },
2532 { ExprRegister[0] , %unknown, 0 },
2533 { ExprConstant[0] , 1, ExprSize8 },
2534 { ExprConstant[0] , 0, ExprSize8 },
2535 };
2536 0000000000000000: 0f b3 20 btr [%rax], %esp
2537 0f b3 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o NaClIllegal
2538 Btr $Ev, $Gv
2539 E_Operand OpUse OpSet
2540 G_Operand OpUse
2541 NaClExpVector[8] = {
2542 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2543 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2544 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2545 { ExprRegister[0] , %unknown, 0 },
2546 { ExprConstant[0] , 1, ExprSize8 },
2547 { ExprConstant[0] , 0, ExprSize8 },
2548 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2549 { ExprRegister[0] , %esp, ExprUsed | ExprSize32 },
2550 };
2551 0000000000000000: 0f a3 20 bt [%rax], %esp
2552 0f a3 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o NaClIllegal
2553 Bt $Ev, $Gv
2554 E_Operand OpUse
2555 G_Operand OpUse
2556 NaClExpVector[8] = {
2557 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2558 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2559 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2560 { ExprRegister[0] , %unknown, 0 },
2561 { ExprConstant[0] , 1, ExprSize8 },
2562 { ExprConstant[0] , 0, ExprSize8 },
2563 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2564 { ExprRegister[0] , %esp, ExprUsed | ExprSize32 },
2565 };
2566 0000000000000000: 0f bb 20 btc [%rax], %esp
2567 0f bb 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o NaClIllegal
2568 Btc $Ev, $Gv
2569 E_Operand OpUse OpSet
2570 G_Operand OpUse
2571 NaClExpVector[8] = {
2572 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2573 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2574 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2575 { ExprRegister[0] , %unknown, 0 },
2576 { ExprConstant[0] , 1, ExprSize8 },
2577 { ExprConstant[0] , 0, ExprSize8 },
2578 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2579 { ExprRegister[0] , %esp, ExprUsed | ExprSize32 },
2580 };
2581 0000000000000000: 0f ab 20 bts [%rax], %esp
2582 0f ab 386 OpcodeUsesModRm OpcodeLockable OpcodeAllowsDat a16 OperandSize_w OperandSize_v OperandSize_o NaClIllegal
2583 Bts $Ev, $Gv
2584 E_Operand OpUse OpSet
2585 G_Operand OpUse
2586 NaClExpVector[8] = {
2587 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2588 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
2589 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2590 { ExprRegister[0] , %unknown, 0 },
2591 { ExprConstant[0] , 1, ExprSize8 },
2592 { ExprConstant[0] , 0, ExprSize8 },
2593 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2594 { ExprRegister[0] , %esp, ExprUsed | ExprSize32 },
2595 };
2596 0000000000000000: 66 0f 78 c1 02 04 extrq %xmm0, 0x2, 0x4
2597 66 0f 78 / 0 SSE4A OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed _b OpcodeHasImmed2_b OpcodeAllowsData16 SizeIgnoresData16 NaClIllegal
2598 Extrq $Vdq, $Ib, $Ib
2599 Xmm_G_Operand OpUse OpSet AllowGOperandWithOpcodeInModRm
2600 I_Operand OpUse
2601 I2_Operand OpUse
2602 NaClExpVector[6] = {
2603 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2604 { ExprRegister[0] , %xmm0, ExprSet | ExprUsed },
2605 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2606 { ExprConstant[0] , 0x2, ExprUsed | ExprSize8 | ExprUnsignedHex },
2607 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2608 { ExprConstant[0] , 0x4, ExprUsed | ExprSize8 | ExprUnsignedHex },
2609 };
2610 0000000000000000: f2 0f 78 ca 02 04 insertq %xmm1, %x mm2, 0x2, 0x4
2611 f2 0f 78 SSE4A ModRmModIs0x3 OpcodeUsesModRm OpcodeHasImmed _b OpcodeHasImmed2_b OpcodeAllowsRepne
2612 Insertq $Vdq, $VRq, $Ib, $Ib
2613 Xmm_G_Operand OpUse OpSet
2614 Xmm_E_Operand OpUse
2615 I_Operand OpUse
2616 I2_Operand OpUse
2617 NaClExpVector[8] = {
2618 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2619 { ExprRegister[0] , %xmm1, ExprSet | ExprUsed },
2620 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2621 { ExprRegister[0] , %xmm2, ExprUsed },
2622 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2623 { ExprConstant[0] , 0x2, ExprUsed | ExprSize8 | ExprUnsignedHex },
2624 { OperandReference[1] , 3, ExprSize8 | ExprUnsignedInt },
2625 { ExprConstant[0] , 0x4, ExprUsed | ExprSize8 | ExprUnsignedHex },
2626 };
2627 0000000000000000: 66 0f 79 ca extrq %xmm1, %xmm 2
2628 66 0f 79 SSE4A ModRmModIs0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 SizeIgnoresData16
2629 Extrq $Vdq, $VRdq
2630 Xmm_G_Operand OpUse OpSet
2631 Xmm_E_Operand OpUse
2632 NaClExpVector[4] = {
2633 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2634 { ExprRegister[0] , %xmm1, ExprSet | ExprUsed },
2635 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2636 { ExprRegister[0] , %xmm2, ExprUsed },
2637 };
2638 0000000000000000: f2 0f 79 ca insertq %xmm1, %x mm2
2639 f2 0f 79 SSE4A ModRmModIs0x3 OpcodeUsesModRm OpcodeAllowsRe pne
2640 Insertq $Vdq, $VRdq
2641 Xmm_G_Operand OpUse OpSet
2642 Xmm_E_Operand OpUse
2643 NaClExpVector[4] = {
2644 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2645 { ExprRegister[0] , %xmm1, ExprSet | ExprUsed },
2646 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2647 { ExprRegister[0] , %xmm2, ExprUsed },
2648 };
2649 0000000000000000: e9 00 00 01 02 jmp 0x2010005
2650 e9 386 OpcodeHasImmed_v OperandSize_v OperandSize_o O perandSizeDefaultIs64 JumpInstruction
2651 Jmp {%rip}, $Jzd
2652 RegRIP OpSet OpImplicit
2653 J_Operand OpUse OperandNear OperandRelative
2654 NaClExpVector[4] = {
2655 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
2656 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
2657 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2658 { ExprConstant[0] , 0x2010005, ExprUsed | ExprSize32 | ExprSignedHex | ExprJum pTarget },
2659 };
2660 0000000000000000: 67 40 a0 00 01 02 03 mov %al, [0x30201 00]
2661 a0 386 OpcodeHasImmed_Addr OperandSize_b
2662 Mov %al, $Ob
2663 RegAL OpSet
2664 O_Operand OpUse
2665 NaClExpVector[8] = {
2666 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2667 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
2668 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2669 { ExprMemOffset[4] , 0, ExprUsed | ExprSize32 },
2670 { ExprRegister[0] , %unknown, 0 },
2671 { ExprRegister[0] , %unknown, 0 },
2672 { ExprConstant[0] , 1, ExprSize8 },
2673 { ExprConstant[0] , 0x3020100, ExprSize32 | ExprUnsignedHex },
2674 };
2675 0000000000000000: 66 0f 3a 60 00 01 pcmpestrm %xmm0, [%rax], 0x1
2676 66 0f 3a 60 SSE42 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllow sData16 SizeIgnoresData16 OperandSize_v OperandSize_o
2677 Pcmpestrm {%xmm0}, {$rAXv}, {$rDXv}, $Vdq, $Wdq, $Ib
2678 RegXMM0 OpSet OpImplicit
2679 RegREAX OpSet OpImplicit
2680 RegREDX OpSet OpImplicit
2681 Xmm_G_Operand OpUse
2682 Xmm_E_Operand OpUse
2683 I_Operand OpUse
2684 NaClExpVector[16] = {
2685 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
2686 { ExprRegister[0] , %xmm0, ExprSet },
2687 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
2688 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
2689 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt | ExprImplicit },
2690 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
2691 { OperandReference[1] , 3, ExprSize8 | ExprUnsignedInt },
2692 { ExprRegister[0] , %xmm0, ExprUsed },
2693 { OperandReference[1] , 4, ExprSize8 | ExprUnsignedInt },
2694 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2695 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2696 { ExprRegister[0] , %unknown, 0 },
2697 { ExprConstant[0] , 1, ExprSize8 },
2698 { ExprConstant[0] , 0, ExprSize8 },
2699 { OperandReference[1] , 5, ExprSize8 | ExprUnsignedInt },
2700 { ExprConstant[0] , 0x1, ExprUsed | ExprSize8 | ExprUnsignedHex },
2701 };
2702 0000000000000000: 90 nop
2703 [hard coded] 386
2704 Nop
2705 NaClExpVector[0] = {
2706 };
2707 0000000000000000: 66 90 nop
2708 [hard coded] 386
2709 Nop
2710 NaClExpVector[0] = {
2711 };
2712 0000000000000000: 66 66 90 xchg %ax, %ax
2713 90 - r0 386 OpcodePlusR OpcodeLockable OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
2714 Xchg $r8v, $rAXv
2715 G_OpcodeBase OpUse OpSet OperandZeroExtends_v
2716 RegREAX OpUse OpSet OperandZeroExtends_v
2717 NaClExpVector[4] = {
2718 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2719 { ExprRegister[0] , %ax, ExprSet | ExprUsed | ExprSize16 },
2720 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2721 { ExprRegister[0] , %ax, ExprSet | ExprUsed | ExprSize16 },
2722 };
2723 0000000000000000: 8d 76 00 lea %esi, [%rsi]
2724 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
2725 Lea $Gv, $M
2726 G_Operand OpSet OperandZeroExtends_v
2727 M_Operand OpAddress
2728 NaClExpVector[8] = {
2729 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2730 { ExprRegister[0] , %esi, ExprSet | ExprSize32 },
2731 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2732 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
2733 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
2734 { ExprRegister[0] , %unknown, 0 },
2735 { ExprConstant[0] , 1, ExprSize8 },
2736 { ExprConstant[0] , 0x0, ExprSize8 | ExprSignedHex },
2737 };
2738 0000000000000000: 8d 74 26 00 lea %esi, [%rsi]
2739 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
2740 Lea $Gv, $M
2741 G_Operand OpSet OperandZeroExtends_v
2742 M_Operand OpAddress
2743 NaClExpVector[8] = {
2744 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2745 { ExprRegister[0] , %esi, ExprSet | ExprSize32 },
2746 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2747 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
2748 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
2749 { ExprRegister[0] , %unknown, 0 },
2750 { ExprConstant[0] , 1, ExprSize8 },
2751 { ExprConstant[0] , 0x0, ExprSize8 | ExprSignedHex },
2752 };
2753 0000000000000000: 8d b6 00 00 00 00 lea %esi, [%rsi]
2754 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
2755 Lea $Gv, $M
2756 G_Operand OpSet OperandZeroExtends_v
2757 M_Operand OpAddress
2758 NaClExpVector[8] = {
2759 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2760 { ExprRegister[0] , %esi, ExprSet | ExprSize32 },
2761 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2762 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
2763 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
2764 { ExprRegister[0] , %unknown, 0 },
2765 { ExprConstant[0] , 1, ExprSize8 },
2766 { ExprConstant[0] , 0x0, ExprSize32 | ExprSignedHex },
2767 };
2768 0000000000000000: 8d b4 26 00 00 00 00 lea %esi, [%rsi]
2769 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
2770 Lea $Gv, $M
2771 G_Operand OpSet OperandZeroExtends_v
2772 M_Operand OpAddress
2773 NaClExpVector[8] = {
2774 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2775 { ExprRegister[0] , %esi, ExprSet | ExprSize32 },
2776 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2777 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
2778 { ExprRegister[0] , %rsi, ExprUsed | ExprSize64 },
2779 { ExprRegister[0] , %unknown, 0 },
2780 { ExprConstant[0] , 1, ExprSize8 },
2781 { ExprConstant[0] , 0x0, ExprSize32 | ExprSignedHex },
2782 };
2783 0000000000000000: 89 f6 mov %esi, %esi
2784 89 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
2785 Mov $Ev, $Gv
2786 E_Operand OpSet OperandZeroExtends_v
2787 G_Operand OpUse
2788 NaClExpVector[4] = {
2789 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2790 { ExprRegister[0] , %esi, ExprSet | ExprSize32 },
2791 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2792 { ExprRegister[0] , %esi, ExprUsed | ExprSize32 },
2793 };
2794 0000000000000000: 8d bc 27 00 00 00 00 lea %edi, [%rdi]
2795 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
2796 Lea $Gv, $M
2797 G_Operand OpSet OperandZeroExtends_v
2798 M_Operand OpAddress
2799 NaClExpVector[8] = {
2800 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2801 { ExprRegister[0] , %edi, ExprSet | ExprSize32 },
2802 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2803 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
2804 { ExprRegister[0] , %rdi, ExprUsed | ExprSize64 },
2805 { ExprRegister[0] , %unknown, 0 },
2806 { ExprConstant[0] , 1, ExprSize8 },
2807 { ExprConstant[0] , 0x0, ExprSize32 | ExprSignedHex },
2808 };
2809 0000000000000000: 0f 1f 00 nop
2810 [hard coded] 386
2811 Nop
2812 NaClExpVector[0] = {
2813 };
2814 0000000000000000: 0f 1f 40 00 nop
2815 [hard coded] 386
2816 Nop
2817 NaClExpVector[0] = {
2818 };
2819 0000000000000000: 0f 1f 44 00 00 nop
2820 [hard coded] 386
2821 Nop
2822 NaClExpVector[0] = {
2823 };
2824 0000000000000000: 66 0f 1f 44 00 00 nop
2825 [hard coded] 386
2826 Nop
2827 NaClExpVector[0] = {
2828 };
2829 0000000000000000: 0f 1f 80 00 00 00 00 nop
2830 [hard coded] 386
2831 Nop
2832 NaClExpVector[0] = {
2833 };
2834 0000000000000000: 0f 1f 84 00 00 00 00 00 nop
2835 [hard coded] 386
2836 Nop
2837 NaClExpVector[0] = {
2838 };
2839 0000000000000000: 66 0f 1f 84 00 00 00 00 00 nop
2840 [hard coded] 386
2841 Nop
2842 NaClExpVector[0] = {
2843 };
2844 0000000000000000: 66 2e 0f 1f 84 00 00 00 00 00 nop
2845 [hard coded] 386
2846 Nop
2847 NaClExpVector[0] = {
2848 };
2849 0000000000000000: 66 66 2e 0f 1f 84 00 00 00 00 00 nop
2850 [hard coded] 386
2851 Nop
2852 NaClExpVector[0] = {
2853 };
2854 0000000000000000: 66 66 66 2e 0f 1f 84 00 00 00 00 00 nop
2855 [hard coded] 386
2856 Nop
2857 NaClExpVector[0] = {
2858 };
2859 0000000000000000: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nop
2860 [hard coded] 386
2861 Nop
2862 NaClExpVector[0] = {
2863 };
2864 0000000000000000: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nop
2865 [hard coded] 386
2866 Nop
2867 NaClExpVector[0] = {
2868 };
2869 0000000000000000: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nop
2870 [hard coded] 386
2871 Nop
2872 NaClExpVector[0] = {
2873 };
2874 0000000000000000: 41 ff 74 3f 20 push [%r15+%rdi*1 +0x20]
2875 ff / 6 386 OpcodeInModRm OpcodeUsesModRm OpcodeAllowsData 16 OperandSize_w OperandSize_v OperandSize_o OperandSizeDefaultIs64
2876 Push {%rsp}, $Ev
2877 RegRSP OpUse OpSet OpImplicit
2878 E_Operand OpUse
2879 NaClExpVector[8] = {
2880 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
2881 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
2882 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2883 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2884 { ExprRegister[0] , %r15, ExprUsed | ExprSize64 },
2885 { ExprRegister[0] , %rdi, ExprUsed | ExprSize64 },
2886 { ExprConstant[0] , 1, ExprSize8 },
2887 { ExprConstant[0] , 0x20, ExprSize8 | ExprSignedHex },
2888 };
2889 0000000000000000: 0f 0b ud2
2890 [hard coded] 386
2891 Ud2
2892 NaClExpVector[0] = {
2893 };
2894 0000000000000000: 0f 70 00 00 pshufw %mmx0, [%r ax], 0x0
2895 0f 70 MMX OpcodeUsesModRm OpcodeHasImmed_b
2896 Pshufw $Pq, $Qq, $Ib
2897 Mmx_G_Operand OpSet
2898 Mmx_E_Operand OpUse
2899 I_Operand OpUse
2900 NaClExpVector[10] = {
2901 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2902 { ExprRegister[0] , %mmx0, ExprSet },
2903 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2904 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2905 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2906 { ExprRegister[0] , %unknown, 0 },
2907 { ExprConstant[0] , 1, ExprSize8 },
2908 { ExprConstant[0] , 0, ExprSize8 },
2909 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2910 { ExprConstant[0] , 0x0, ExprUsed | ExprSize8 | ExprUnsignedHex },
2911 };
2912 0000000000000000: 0f ae 38 clflush [%rax]
2913 0f ae / 7 SFENCE_CLFLUSH OpcodeInModRm ModRmModIsnt0x3 Opcod eUsesModRm NaClIllegal
2914 Clflush $Mb
2915 Mb_Operand OpUse
2916 NaClExpVector[6] = {
2917 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2918 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2919 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2920 { ExprRegister[0] , %unknown, 0 },
2921 { ExprConstant[0] , 1, ExprSize8 },
2922 { ExprConstant[0] , 0, ExprSize8 },
2923 };
2924 0000000000000000: 0f ae fc invalid
2925 0f ae / 7 / 4 INVALID OpcodeInModRm OpcodeInModRmRm ModRmModIs0x 3 OpcodeUsesModRm NaClIllegal
2926 NaClExpVector[0] = {
2927 };
2928 0000000000000000: 40 dc 20 fsub %st0, [%rax]
2929 dc / 4 X87 OpcodeInModRm ModRmModIsnt0x3 OpcodeUsesModRm
2930 Fsub %st0, $Mq
2931 RegST0 OpUse OpSet
2932 Mo_Operand OpUse
2933 NaClExpVector[8] = {
2934 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2935 { ExprRegister[0] , %st0, ExprSet | ExprUsed },
2936 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2937 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2938 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2939 { ExprRegister[0] , %unknown, 0 },
2940 { ExprConstant[0] , 1, ExprSize8 },
2941 { ExprConstant[0] , 0, ExprSize8 },
2942 };
2943 0000000000000000: 0f ba 20 00 bt [%rax], 0x0
2944 0f ba / 4 386 OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsData16 OperandSize_w OperandSize_v OperandSize_o
2945 Bt $Ev, $Ib
2946 E_Operand OpUse
2947 I_Operand OpUse
2948 NaClExpVector[8] = {
2949 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2950 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2951 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2952 { ExprRegister[0] , %unknown, 0 },
2953 { ExprConstant[0] , 1, ExprSize8 },
2954 { ExprConstant[0] , 0, ExprSize8 },
2955 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2956 { ExprConstant[0] , 0x0, ExprUsed | ExprSize8 | ExprUnsignedHex },
2957 };
2958 0000000000000000: 66 0f 3a 15 00 00 pextrw [%rax], %x mm0, 0x0
2959 66 0f 3a 15 SSE41 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllow sData16 SizeIgnoresData16
2960 Pextrw $Rd/Mw, $Vdq, $Ib
2961 Ev_Operand OpSet
2962 Xmm_G_Operand OpUse
2963 I_Operand OpUse
2964 NaClExpVector[10] = {
2965 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2966 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
2967 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2968 { ExprRegister[0] , %unknown, 0 },
2969 { ExprConstant[0] , 1, ExprSize8 },
2970 { ExprConstant[0] , 0, ExprSize8 },
2971 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2972 { ExprRegister[0] , %xmm0, ExprUsed },
2973 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
2974 { ExprConstant[0] , 0x0, ExprUsed | ExprSize8 | ExprUnsignedHex },
2975 };
2976 0000000000000000: 0f ec 00 paddsb %mmx0, [%r ax]
2977 0f ec MMX OpcodeUsesModRm
2978 Paddsb $Pq, $Qq
2979 Mmx_G_Operand OpUse OpSet
2980 Mmx_E_Operand OpUse
2981 NaClExpVector[8] = {
2982 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2983 { ExprRegister[0] , %mmx0, ExprSet | ExprUsed },
2984 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
2985 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
2986 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
2987 { ExprRegister[0] , %unknown, 0 },
2988 { ExprConstant[0] , 1, ExprSize8 },
2989 { ExprConstant[0] , 0, ExprSize8 },
2990 };
2991 0000000000000000: 0f f4 00 pmuludq %mmx0, [% rax]
2992 0f f4 MMX OpcodeUsesModRm
2993 Pmuludq $Pq, $Qq
2994 Mmx_G_Operand OpUse OpSet
2995 Mmx_E_Operand OpUse
2996 NaClExpVector[8] = {
2997 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
2998 { ExprRegister[0] , %mmx0, ExprSet | ExprUsed },
2999 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3000 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
3001 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3002 { ExprRegister[0] , %unknown, 0 },
3003 { ExprConstant[0] , 1, ExprSize8 },
3004 { ExprConstant[0] , 0, ExprSize8 },
3005 };
3006 0000000000001000: 40 e0 00 loopne 0x1003
3007 e0 386 OpcodeHasImmed OperandSize_b AddressSize_o Con ditionalJump
3008 Loopne {%rip}, {%rcx}, $Jb
3009 RegRIP OpSet OpImplicit
3010 RegRCX OpUse OpSet OpImplicit
3011 J_Operand OpUse OperandNear OperandRelative
3012 NaClExpVector[6] = {
3013 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3014 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
3015 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3016 { ExprRegister[0] , %rcx, ExprSet | ExprUsed | ExprSize64 },
3017 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3018 { ExprConstant[0] , 0x1003, ExprUsed | ExprSize8 | ExprSignedHex | ExprJumpTar get },
3019 };
3020 0000000000000000: 40 e3 00 jrcxz 0x3
3021 e3 386 OpcodeHasImmed OperandSize_b AddressSize_o Con ditionalJump BranchHints
3022 Jrcxz {%rip}, {%rcx}, $Jb
3023 RegRIP OpSet OpImplicit
3024 RegRCX OpUse OpImplicit
3025 J_Operand OpUse OperandNear OperandRelative
3026 NaClExpVector[6] = {
3027 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3028 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
3029 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3030 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
3031 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3032 { ExprConstant[0] , 0x3, ExprUsed | ExprSize8 | ExprSignedHex | ExprJumpTarget },
3033 };
3034 0000000000000000: 67 40 e3 00 jecxz 0x4
3035 e3 386 OpcodeHasImmed OperandSize_b AddressSize_v Con ditionalJump BranchHints
3036 Jecxz {%rip}, {%ecx}, $Jb
3037 RegRIP OpSet OpImplicit
3038 RegECX OpUse OpImplicit
3039 J_Operand OpUse OperandNear OperandRelative
3040 NaClExpVector[6] = {
3041 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3042 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
3043 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3044 { ExprRegister[0] , %ecx, ExprUsed | ExprSize32 },
3045 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3046 { ExprConstant[0] , 0x4, ExprUsed | ExprSize8 | ExprSignedHex | ExprJumpTarget },
3047 };
3048 0000000000000000: 41 d9 f0 f2xm1 %st0
3049 d9 f0 X87
3050 F2xm1 %st0
3051 RegST0 OpUse OpSet
3052 NaClExpVector[2] = {
3053 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3054 { ExprRegister[0] , %st0, ExprSet | ExprUsed },
3055 };
3056 0000000000000000: 66 0f 52 invalid
3057 66 0f 52 INVALID OpcodeAllowsData16 SizeIgnoresData16 NaClI llegal
3058 NaClExpVector[0] = {
3059 };
3060 0000000000000000: 66 0f 53 invalid
3061 66 0f 53 INVALID OpcodeAllowsData16 SizeIgnoresData16 NaClI llegal
3062 NaClExpVector[0] = {
3063 };
3064 0000000000000000: f2 0f 52 invalid
3065 f2 0f 52 INVALID OpcodeAllowsRepne NaClIllegal
3066 NaClExpVector[0] = {
3067 };
3068 0000000000000000: f2 0f 53 invalid
3069 f2 0f 53 INVALID OpcodeAllowsRepne NaClIllegal
3070 NaClExpVector[0] = {
3071 };
3072 0000000000000000: 66 0f 78 00 00 00 extrq %xmm0, 0x0, 0x0
3073 66 0f 78 / 0 SSE4A OpcodeInModRm OpcodeUsesModRm OpcodeHasImmed _b OpcodeHasImmed2_b OpcodeAllowsData16 SizeIgnoresData16 NaClIllegal
3074 Extrq $Vdq, $Ib, $Ib
3075 Xmm_G_Operand OpUse OpSet AllowGOperandWithOpcodeInModRm
3076 I_Operand OpUse
3077 I2_Operand OpUse
3078 NaClExpVector[6] = {
3079 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3080 { ExprRegister[0] , %xmm0, ExprSet | ExprUsed },
3081 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3082 { ExprConstant[0] , 0x0, ExprUsed | ExprSize8 | ExprUnsignedHex },
3083 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3084 { ExprConstant[0] , 0x0, ExprUsed | ExprSize8 | ExprUnsignedHex },
3085 };
3086 0000000000000000: 26 e8 00 01 02 03 call 0x3020106
3087 e8 386 OpcodeHasImmed_v OperandSize_v OperandSize_o O perandSizeDefaultIs64 JumpInstruction
3088 Call {%rip}, {%rsp}, $Jzd
3089 RegRIP OpUse OpSet OpImplicit
3090 RegRSP OpUse OpSet OpImplicit
3091 J_Operand OpUse OperandNear OperandRelative
3092 NaClExpVector[6] = {
3093 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3094 { ExprRegister[0] , %rip, ExprSet | ExprUsed | ExprSize64 },
3095 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3096 { ExprRegister[0] , %rsp, ExprSet | ExprUsed | ExprSize64 },
3097 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3098 { ExprConstant[0] , 0x3020106, ExprUsed | ExprSize32 | ExprSignedHex | ExprJum pTarget },
3099 };
3100 0000000000000000: 0f a4 c6 01 shld %esi, %eax, 0x1
3101 0f a4 386 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsD ata16 OperandSize_w OperandSize_v OperandSize_o
3102 Shld $Ev, $Gv, $Ib
3103 E_Operand OpSet
3104 G_Operand OpUse
3105 I_Operand OpUse
3106 NaClExpVector[6] = {
3107 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3108 { ExprRegister[0] , %esi, ExprSet | ExprSize32 },
3109 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3110 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
3111 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3112 { ExprConstant[0] , 0x1, ExprUsed | ExprSize8 | ExprUnsignedHex },
3113 };
3114 0000000000000000: 0f a5 c6 shld %esi, %eax, %cl
3115 0f a5 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
3116 Shld $Ev, $Gv, %cl
3117 E_Operand OpSet
3118 G_Operand OpUse
3119 RegCL OpUse
3120 NaClExpVector[6] = {
3121 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3122 { ExprRegister[0] , %esi, ExprSet | ExprSize32 },
3123 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3124 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
3125 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3126 { ExprRegister[0] , %cl, ExprUsed | ExprSize8 },
3127 };
3128 0000000000000000: 48 0f a5 c6 shld %rsi, %rax, %cl
3129 0f a5 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
3130 Shld $Ev, $Gv, %cl
3131 E_Operand OpSet
3132 G_Operand OpUse
3133 RegCL OpUse
3134 NaClExpVector[6] = {
3135 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3136 { ExprRegister[0] , %rsi, ExprSet | ExprSize64 },
3137 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3138 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3139 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3140 { ExprRegister[0] , %cl, ExprUsed | ExprSize8 },
3141 };
3142 0000000000000000: 0f 16 d1 movlhps %xmm2, %x mm1
3143 0f 16 SSE ModRmModIs0x3 OpcodeUsesModRm
3144 Movlhps $Vps, $VRq
3145 Xmm_G_Operand OpSet
3146 Xmm_E_Operand OpUse
3147 NaClExpVector[4] = {
3148 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3149 { ExprRegister[0] , %xmm2, ExprSet },
3150 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3151 { ExprRegister[0] , %xmm1, ExprUsed },
3152 };
3153 0000000000000000: 0f 16 a5 00 00 00 00 movhps %xmm4, [%r bp]
3154 0f 16 SSE ModRmModIsnt0x3 OpcodeUsesModRm
3155 Movhps $Vps, $Mq
3156 Xmm_G_Operand OpSet
3157 Mo_Operand OpUse
3158 NaClExpVector[8] = {
3159 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3160 { ExprRegister[0] , %xmm4, ExprSet },
3161 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3162 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
3163 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
3164 { ExprRegister[0] , %unknown, 0 },
3165 { ExprConstant[0] , 1, ExprSize8 },
3166 { ExprConstant[0] , 0x0, ExprSize32 | ExprSignedHex },
3167 };
3168 0000000000000000: 0f 12 e8 movhlps %xmm5, %x mm0
3169 0f 12 SSE ModRmModIs0x3 OpcodeUsesModRm
3170 Movhlps $Vps, $VRq
3171 Xmm_G_Operand OpSet
3172 Xmm_E_Operand OpUse
3173 NaClExpVector[4] = {
3174 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3175 { ExprRegister[0] , %xmm5, ExprSet },
3176 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3177 { ExprRegister[0] , %xmm0, ExprUsed },
3178 };
3179 0000000000000000: 0f 12 0c 17 movlps %xmm1, [%r di+%rdx*1]
3180 0f 12 SSE ModRmModIsnt0x3 OpcodeUsesModRm
3181 Movlps $Vps, $Mq
3182 Xmm_G_Operand OpSet
3183 Mo_Operand OpUse
3184 NaClExpVector[8] = {
3185 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3186 { ExprRegister[0] , %xmm1, ExprSet },
3187 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3188 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
3189 { ExprRegister[0] , %rdi, ExprUsed | ExprSize64 },
3190 { ExprRegister[0] , %rdx, ExprUsed | ExprSize64 },
3191 { ExprConstant[0] , 1, ExprSize8 },
3192 { ExprConstant[0] , 0, ExprSize8 },
3193 };
3194 0000000000000000: 41 0f 12 0c 17 movlps %xmm1, [%r 15+%rdx*1]
3195 0f 12 SSE ModRmModIsnt0x3 OpcodeUsesModRm
3196 Movlps $Vps, $Mq
3197 Xmm_G_Operand OpSet
3198 Mo_Operand OpUse
3199 NaClExpVector[8] = {
3200 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3201 { ExprRegister[0] , %xmm1, ExprSet },
3202 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3203 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
3204 { ExprRegister[0] , %r15, ExprUsed | ExprSize64 },
3205 { ExprRegister[0] , %rdx, ExprUsed | ExprSize64 },
3206 { ExprConstant[0] , 1, ExprSize8 },
3207 { ExprConstant[0] , 0, ExprSize8 },
3208 };
3209 0000000000000000: 0f c6 d2 00 shufps %xmm2, %xm m2, 0x0
3210 0f c6 SSE OpcodeUsesModRm OpcodeHasImmed_b
3211 Shufps $Vps, $Wps, $Ib
3212 Xmm_G_Operand OpUse OpSet
3213 Xmm_E_Operand OpUse
3214 I_Operand OpUse
3215 NaClExpVector[6] = {
3216 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3217 { ExprRegister[0] , %xmm2, ExprSet | ExprUsed },
3218 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3219 { ExprRegister[0] , %xmm2, ExprUsed },
3220 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3221 { ExprConstant[0] , 0x0, ExprUsed | ExprSize8 | ExprUnsignedHex },
3222 };
3223 0000000000000000: 66 0f c6 d2 00 shufpd %xmm2, %xm m2, 0x0
3224 66 0f c6 SSE2 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllows Data16 SizeIgnoresData16
3225 Shufpd $Vpd, $Wpd, $Ib
3226 Xmm_G_Operand OpUse OpSet
3227 Xmm_E_Operand OpUse
3228 I_Operand OpUse
3229 NaClExpVector[6] = {
3230 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3231 { ExprRegister[0] , %xmm2, ExprSet | ExprUsed },
3232 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3233 { ExprRegister[0] , %xmm2, ExprUsed },
3234 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3235 { ExprConstant[0] , 0x0, ExprUsed | ExprSize8 | ExprUnsignedHex },
3236 };
3237 0000000000000000: 66 43 0f be 04 27 movsx %ax, [%r15+ %r12*1]
3238 0f be 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
3239 Movsx $Gv, $Eb
3240 G_Operand OpSet OperandZeroExtends_v
3241 Eb_Operand OpUse
3242 NaClExpVector[8] = {
3243 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3244 { ExprRegister[0] , %ax, ExprSet | ExprSize16 },
3245 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3246 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
3247 { ExprRegister[0] , %r15, ExprUsed | ExprSize64 },
3248 { ExprRegister[0] , %r12, ExprUsed | ExprSize64 },
3249 { ExprConstant[0] , 1, ExprSize8 },
3250 { ExprConstant[0] , 0, ExprSize8 },
3251 };
3252 0000000000000000: 0f 30 wrmsr
3253 0f 30 RDMSR NaClIllegal
3254 Wrmsr {%eax}, {%edx}, {%ecx}
3255 RegEAX OpUse OpImplicit
3256 RegEDX OpUse OpImplicit
3257 RegECX OpUse OpImplicit
3258 NaClExpVector[6] = {
3259 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3260 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
3261 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3262 { ExprRegister[0] , %edx, ExprUsed | ExprSize32 },
3263 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3264 { ExprRegister[0] , %ecx, ExprUsed | ExprSize32 },
3265 };
3266 0000000000000000: 0f 31 rdtsc
3267 0f 31 RDTSC
3268 Rdtsc {%eax}, {%edx}
3269 RegEAX OpSet OpImplicit
3270 RegEDX OpSet OpImplicit
3271 NaClExpVector[4] = {
3272 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3273 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
3274 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3275 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
3276 };
3277 0000000000000000: 0f 32 rdmsr
3278 0f 32 RDMSR NaClIllegal
3279 Rdmsr {%eax}, {%edx}, {%ecx}
3280 RegEAX OpSet OpImplicit
3281 RegEDX OpSet OpImplicit
3282 RegECX OpUse OpImplicit
3283 NaClExpVector[6] = {
3284 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3285 { ExprRegister[0] , %eax, ExprSet | ExprSize32 },
3286 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3287 { ExprRegister[0] , %edx, ExprSet | ExprSize32 },
3288 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3289 { ExprRegister[0] , %ecx, ExprUsed | ExprSize32 },
3290 };
3291 0000000000000000: 48 0f ac c1 10 shrd %rcx, %rax, 0x10
3292 0f ac 386 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsD ata16 OperandSize_w OperandSize_v OperandSize_o
3293 Shrd $Ev, $Gv, $Ib
3294 E_Operand OpUse OpSet
3295 G_Operand OpUse
3296 I_Operand OpUse
3297 NaClExpVector[6] = {
3298 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3299 { ExprRegister[0] , %rcx, ExprSet | ExprUsed | ExprSize64 },
3300 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3301 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3302 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3303 { ExprConstant[0] , 0x10, ExprUsed | ExprSize8 | ExprUnsignedHex },
3304 };
3305 0000000000000000: 0f ac c1 10 shrd %ecx, %eax, 0x10
3306 0f ac 386 OpcodeUsesModRm OpcodeHasImmed_b OpcodeAllowsD ata16 OperandSize_w OperandSize_v OperandSize_o
3307 Shrd $Ev, $Gv, $Ib
3308 E_Operand OpUse OpSet
3309 G_Operand OpUse
3310 I_Operand OpUse
3311 NaClExpVector[6] = {
3312 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3313 { ExprRegister[0] , %ecx, ExprSet | ExprUsed | ExprSize32 },
3314 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3315 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
3316 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3317 { ExprConstant[0] , 0x10, ExprUsed | ExprSize8 | ExprUnsignedHex },
3318 };
3319 0000000000000000: 0f ad 45 bc shrd [%rbp-0x44], %eax, %cl
3320 0f ad 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
3321 Shrd $Ev, $Gv, %cl
3322 E_Operand OpUse OpSet
3323 G_Operand OpUse
3324 RegCL OpUse
3325 NaClExpVector[10] = {
3326 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3327 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
3328 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
3329 { ExprRegister[0] , %unknown, 0 },
3330 { ExprConstant[0] , 1, ExprSize8 },
3331 { ExprConstant[0] , -0x44, ExprSize8 | ExprSignedHex },
3332 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3333 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
3334 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3335 { ExprRegister[0] , %cl, ExprUsed | ExprSize8 },
3336 };
3337 0000000000000000: 48 0f ad 45 bc shrd [%rbp-0x44], %rax, %cl
3338 0f ad 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o
3339 Shrd $Ev, $Gv, %cl
3340 E_Operand OpUse OpSet
3341 G_Operand OpUse
3342 RegCL OpUse
3343 NaClExpVector[10] = {
3344 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3345 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
3346 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
3347 { ExprRegister[0] , %unknown, 0 },
3348 { ExprConstant[0] , 1, ExprSize8 },
3349 { ExprConstant[0] , -0x44, ExprSize8 | ExprSignedHex },
3350 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3351 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3352 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3353 { ExprRegister[0] , %cl, ExprUsed | ExprSize8 },
3354 };
3355 0000000000000000: 8c 00 mov [%rax], %es
3356 8c 386 ModRmRegSOperand OpcodeUsesModRm OpcodeAllowsD ata16 OperandSize_w OperandSize_v OperandSize_o NaClIllegal
3357 Mov $Mw/Rv, $Sw
3358 E_Operand OpSet OperandZeroExtends_v
3359 S_Operand OpUse
3360 NaClExpVector[8] = {
3361 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3362 { ExprMemOffset[4] , 0, ExprSet | ExprSize64 },
3363 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3364 { ExprRegister[0] , %unknown, 0 },
3365 { ExprConstant[0] , 1, ExprSize8 },
3366 { ExprConstant[0] , 0, ExprSize8 },
3367 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3368 { ExprRegister[0] , %es, ExprUsed | ExprSize16 },
3369 };
3370 0000000000000000: 64 48 8e 00 mov %es, %fs:[%ra x]
3371 8e 386 ModRmRegSOperand OpcodeUsesModRm NaClIllegal
3372 Mov $Sw, $Ew
3373 S_Operand OpSet
3374 Ew_Operand OpUse
3375 NaClExpVector[10] = {
3376 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3377 { ExprRegister[0] , %es, ExprSet | ExprSize16 },
3378 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3379 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 },
3380 { ExprRegister[0] , %fs, ExprUsed | ExprSize16 },
3381 { ExprMemOffset[4] , 0, ExprSize64 },
3382 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3383 { ExprRegister[0] , %unknown, 0 },
3384 { ExprConstant[0] , 1, ExprSize8 },
3385 { ExprConstant[0] , 0, ExprSize8 },
3386 };
3387 0000000000000000: 26 64 65 00 01 add %gs:[%rcx], % al
3388 00 386 OpcodeUsesModRm OpcodeLockable OperandSize_b
3389 Add $Eb, $Gb
3390 E_Operand OpUse OpSet
3391 G_Operand OpUse
3392 NaClExpVector[10] = {
3393 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3394 { ExprSegmentAddress[2] , 0, ExprSet | ExprUsed | ExprSize64 },
3395 { ExprRegister[0] , %gs, ExprUsed | ExprSize16 },
3396 { ExprMemOffset[4] , 0, ExprSize64 },
3397 { ExprRegister[0] , %rcx, ExprUsed | ExprSize64 },
3398 { ExprRegister[0] , %unknown, 0 },
3399 { ExprConstant[0] , 1, ExprSize8 },
3400 { ExprConstant[0] , 0, ExprSize8 },
3401 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3402 { ExprRegister[0] , %al, ExprUsed | ExprSize8 },
3403 };
3404 0000000000000000: 0f a3 00 bt [%rax], %eax
3405 0f a3 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o NaClIllegal
3406 Bt $Ev, $Gv
3407 E_Operand OpUse
3408 G_Operand OpUse
3409 NaClExpVector[8] = {
3410 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3411 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
3412 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3413 { ExprRegister[0] , %unknown, 0 },
3414 { ExprConstant[0] , 1, ExprSize8 },
3415 { ExprConstant[0] , 0, ExprSize8 },
3416 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3417 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
3418 };
3419 0000000000000000: 0f a3 04 00 bt [%rax+%rax*1], %eax
3420 0f a3 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o NaClIllegal
3421 Bt $Ev, $Gv
3422 E_Operand OpUse
3423 G_Operand OpUse
3424 NaClExpVector[8] = {
3425 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3426 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
3427 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3428 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3429 { ExprConstant[0] , 1, ExprSize8 },
3430 { ExprConstant[0] , 0, ExprSize8 },
3431 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3432 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
3433 };
3434 0000000000000000: 0f a3 80 00 01 02 03 bt [%rax+0x302010 0], %eax
3435 0f a3 386 OpcodeUsesModRm OpcodeAllowsData16 OperandSize _w OperandSize_v OperandSize_o NaClIllegal
3436 Bt $Ev, $Gv
3437 E_Operand OpUse
3438 G_Operand OpUse
3439 NaClExpVector[8] = {
3440 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3441 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
3442 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3443 { ExprRegister[0] , %unknown, 0 },
3444 { ExprConstant[0] , 1, ExprSize8 },
3445 { ExprConstant[0] , 0x3020100, ExprSize32 | ExprSignedHex },
3446 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3447 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
3448 };
3449 0000000000000000: 36 64 6f outsd %fs
3450 6f 386 OpcodeAllowsRep OperandSize_v OperandSize_o Na ClIllegal
3451 Outsd {%dx}, {$Xzd}
3452 RegDX OpUse OpImplicit
3453 RegDS_ESI OpUse OpImplicit
3454 NaClExpVector[6] = {
3455 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3456 { ExprRegister[0] , %dx, ExprUsed | ExprSize16 },
3457 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3458 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 | ExprDSrCase },
3459 { ExprRegister[0] , %fs, ExprSize16 },
3460 { ExprRegister[0] , %rsi, ExprSize64 },
3461 };
3462 0000000000000000: 64 40 a0 00 01 02 03 04 05 06 07 mov %al, %fs:[0x7 06050403020100]
3463 a0 386 OpcodeHasImmed_Addr OperandSize_b
3464 Mov %al, $Ob
3465 RegAL OpSet
3466 O_Operand OpUse
3467 NaClExpVector[10] = {
3468 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3469 { ExprRegister[0] , %al, ExprSet | ExprSize8 },
3470 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3471 { ExprSegmentAddress[2] , 0, ExprUsed | ExprSize64 },
3472 { ExprRegister[0] , %fs, ExprUsed | ExprSize16 },
3473 { ExprMemOffset[4] , 0, ExprSize64 },
3474 { ExprRegister[0] , %unknown, 0 },
3475 { ExprRegister[0] , %unknown, 0 },
3476 { ExprConstant[0] , 1, ExprSize8 },
3477 { ExprConstant[0] , 0x706050403020100, ExprSize64 | ExprUnsignedHex },
3478 };
3479 0000000000000000: 0f 01 c8 monitor %eax, %ec x, %edx
3480 0f 01 / 1 / 0 SYSTEM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 OpcodeUsesModRm NaClIllegal
3481 Monitor %reax, %ecx, %edx
3482 RegREAX OpUse
3483 RegECX OpUse
3484 RegEDX OpUse
3485 NaClExpVector[6] = {
3486 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3487 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
3488 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3489 { ExprRegister[0] , %ecx, ExprUsed | ExprSize32 },
3490 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3491 { ExprRegister[0] , %edx, ExprUsed | ExprSize32 },
3492 };
3493 0000000000000000: 0f 01 c9 mwait %eax, %ecx
3494 0f 01 / 1 / 1 SYSTEM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 OpcodeUsesModRm NaClIllegal
3495 Mwait %eax, %ecx
3496 RegEAX
3497 RegECX
3498 NaClExpVector[4] = {
3499 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3500 { ExprRegister[0] , %eax, ExprSize32 },
3501 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3502 { ExprRegister[0] , %ecx, ExprSize32 },
3503 };
3504 0000000000000000: 0f 01 f8 swapgs
3505 0f 01 / 7 / 0 SYSTEM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 OpcodeUsesModRm NaClIllegal LongMode
3506 Swapgs {%gs}
3507 RegGS OpSet OpImplicit
3508 NaClExpVector[2] = {
3509 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3510 { ExprRegister[0] , %gs, ExprSet | ExprSize16 },
3511 };
3512 0000000000000000: 0f 01 f9 rdtscp
3513 0f 01 / 7 / 1 RDTSCP OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 OpcodeUsesModRm NaClIllegal
3514 Rdtscp {%rdx}, {%rax}, {%rcx}
3515 RegRDX OpSet OpImplicit
3516 RegRAX OpSet OpImplicit
3517 RegRCX OpSet OpImplicit
3518 NaClExpVector[6] = {
3519 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3520 { ExprRegister[0] , %rdx, ExprSet | ExprSize64 },
3521 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3522 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
3523 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3524 { ExprRegister[0] , %rcx, ExprSet | ExprSize64 },
3525 };
3526 0000000000000000: 0f 01 d8 vmrun %rax
3527 0f 01 / 3 / 0 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal
3528 Vmrun $rAXva
3529 RegREAXa OpUse
3530 NaClExpVector[2] = {
3531 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3532 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3533 };
3534 0000000000000000: 0f 01 d9 vmmcall
3535 0f 01 / 3 / 1 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal
3536 Vmmcall
3537 NaClExpVector[0] = {
3538 };
3539 0000000000000000: 0f 01 da vmload %rax
3540 0f 01 / 3 / 2 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal
3541 Vmload $rAXva
3542 RegREAXa OpUse
3543 NaClExpVector[2] = {
3544 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3545 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3546 };
3547 0000000000000000: 0f 01 db vmsave %rax
3548 0f 01 / 3 / 3 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal
3549 Vmsave $rAXva
3550 RegREAXa OpUse
3551 NaClExpVector[2] = {
3552 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3553 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3554 };
3555 0000000000000000: 0f 01 dc stgi
3556 0f 01 / 3 / 4 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal
3557 Stgi
3558 NaClExpVector[0] = {
3559 };
3560 0000000000000000: 0f 01 dd clgi
3561 0f 01 / 3 / 5 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal
3562 Clgi
3563 NaClExpVector[0] = {
3564 };
3565 0000000000000000: 0f 01 de skinit %eax
3566 0f 01 / 3 / 6 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal
3567 Skinit {%eip}, %eax
3568 RegEIP OpSet OpImplicit
3569 RegEAX OpUse
3570 NaClExpVector[4] = {
3571 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3572 { ExprRegister[0] , %eip, ExprSet | ExprSize32 },
3573 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3574 { ExprRegister[0] , %eax, ExprUsed | ExprSize32 },
3575 };
3576 0000000000000000: 0f 01 df invlpga %rax, %ec x
3577 0f 01 / 3 / 7 SVM OpcodeInModRm OpcodeInModRmRm ModRmModIs0x3 Op codeUsesModRm NaClIllegal
3578 Invlpga $rAXva, %ecx
3579 RegREAXa OpUse
3580 RegECX OpUse
3581 NaClExpVector[4] = {
3582 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3583 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3584 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3585 { ExprRegister[0] , %ecx, ExprUsed | ExprSize32 },
3586 };
3587 0000000000000000: 0f 20 c0 mov %rax, %cr0
3588 0f 20 SYSTEM ModRmModIs0x3 OpcodeUsesModRm NaClIllegal
3589 Mov $Rd/q, $Cd/q
3590 Eo_Operand OpSet
3591 C_Operand OpUse
3592 NaClExpVector[4] = {
3593 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3594 { ExprRegister[0] , %rax, ExprSet | ExprSize64 },
3595 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3596 { ExprRegister[0] , %cr0, ExprUsed },
3597 };
3598 0000000000000000: 0f 21 f3 mov %rbx, %dr3
3599 0f 21 SYSTEM ModRmModIs0x3 OpcodeUsesModRm NaClIllegal
3600 Mov $Rd/q, $Dd/q
3601 Eo_Operand OpSet
3602 D_Operand OpUse
3603 NaClExpVector[4] = {
3604 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3605 { ExprRegister[0] , %rbx, ExprSet | ExprSize64 },
3606 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3607 { ExprRegister[0] , %dr3, ExprUsed },
3608 };
3609 0000000000000000: 0f 22 cd mov %cr5, %rbp
3610 0f 22 SYSTEM ModRmModIs0x3 OpcodeUsesModRm NaClIllegal
3611 Mov $Cd/q, $Rd/q
3612 C_Operand OpSet
3613 Eo_Operand OpUse
3614 NaClExpVector[4] = {
3615 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3616 { ExprRegister[0] , %cr5, ExprSet },
3617 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3618 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
3619 };
3620 0000000000000000: 0f 23 dd mov %dr5, %rbp
3621 0f 23 SYSTEM ModRmModIs0x3 OpcodeUsesModRm NaClIllegal
3622 Mov $Dd/q, $Rd/q
3623 D_Operand OpSet
3624 Eo_Operand OpUse
3625 NaClExpVector[4] = {
3626 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3627 { ExprRegister[0] , %dr5, ExprSet },
3628 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3629 { ExprRegister[0] , %rbp, ExprUsed | ExprSize64 },
3630 };
3631 0000000000000000: 0f 0f 00 00 invalid %mmx0, [% rax], 0x0
3632 0f 0f INVALID Opcode0F0F OpcodeUsesModRm OpcodeHasImmed_ b NaClIllegal
3633 Invalid $Pq, $Qq, $Ib
3634 Mmx_G_Operand
3635 Mmx_E_Operand
3636 I_Operand
3637 NaClExpVector[10] = {
3638 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3639 { ExprRegister[0] , %mmx0, 0 },
3640 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3641 { ExprMemOffset[4] , 0, ExprSize64 },
3642 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3643 { ExprRegister[0] , %unknown, 0 },
3644 { ExprConstant[0] , 1, ExprSize8 },
3645 { ExprConstant[0] , 0, ExprSize8 },
3646 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3647 { ExprConstant[0] , 0x0, ExprSize8 | ExprUnsignedHex },
3648 };
3649 0000000000000000: 0f 0f 00 90 pfcmpge %mmx0, [% rax]
3650 0f 0f 90 3DNOW OpcodeUsesModRm
3651 Pfcmpge $Pq, $Qq
3652 Mmx_G_Operand OpUse OpSet
3653 Mmx_E_Operand OpUse
3654 NaClExpVector[8] = {
3655 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3656 { ExprRegister[0] , %mmx0, ExprSet | ExprUsed },
3657 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3658 { ExprMemOffset[4] , 0, ExprUsed | ExprSize64 },
3659 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3660 { ExprRegister[0] , %unknown, 0 },
3661 { ExprConstant[0] , 1, ExprSize8 },
3662 { ExprConstant[0] , 0, ExprSize8 },
3663 };
3664 0000000000000000: 8d bf 00 00 00 00 lea %edi, [%rdi]
3665 8d 386 ModRmModIsnt0x3 OpcodeUsesModRm OpcodeAllowsDa ta16 OperandSize_w OperandSize_v OperandSize_o
3666 Lea $Gv, $M
3667 G_Operand OpSet OperandZeroExtends_v
3668 M_Operand OpAddress
3669 NaClExpVector[8] = {
3670 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3671 { ExprRegister[0] , %edi, ExprSet | ExprSize32 },
3672 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3673 { ExprMemOffset[4] , 0, ExprAddress | ExprSize64 },
3674 { ExprRegister[0] , %rdi, ExprUsed | ExprSize64 },
3675 { ExprRegister[0] , %unknown, 0 },
3676 { ExprConstant[0] , 1, ExprSize8 },
3677 { ExprConstant[0] , 0x0, ExprSize32 | ExprSignedHex },
3678 };
3679 0000000000000000: eb 1d jmp 0x1f
3680 eb 386 OpcodeHasImmed OperandSize_b JumpInstruction
3681 Jmp {%rip}, $Jb
3682 RegRIP OpSet OpImplicit
3683 J_Operand OpUse OperandNear OperandRelative
3684 NaClExpVector[4] = {
3685 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3686 { ExprRegister[0] , %rip, ExprSet | ExprSize64 },
3687 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3688 { ExprConstant[0] , 0x1f, ExprUsed | ExprSize8 | ExprSignedHex | ExprJumpTarge t },
3689 };
3690 0000000000000000: f0 0f c7 08 cmpxchg8b [%rax]
3691 0f c7 / 1 CMPXCHG8B OpcodeInModRm ModRmModIsnt0x3 OpcodeUses ModRm OpcodeLockable OperandSize_v
3692 Cmpxchg8b {%edx}, {%eax}, $Mq
3693 RegEDX OpUse OpSet OpImplicit
3694 RegEAX OpUse OpSet OpImplicit
3695 Mo_Operand OpUse OpSet
3696 NaClExpVector[10] = {
3697 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3698 { ExprRegister[0] , %edx, ExprSet | ExprUsed | ExprSize32 },
3699 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3700 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
3701 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3702 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
3703 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3704 { ExprRegister[0] , %unknown, 0 },
3705 { ExprConstant[0] , 1, ExprSize8 },
3706 { ExprConstant[0] , 0, ExprSize8 },
3707 };
3708 0000000000000000: 48 f0 0f c7 08 cmpxchg16b [%rax]
3709 0f c7 / 1 CMPXCHG16B OpcodeInModRm ModRmModIsnt0x3 OpcodeUse sModRm OpcodeLockable OperandSize_o
3710 Cmpxchg16b {%rdx}, {%eax}, $Mdq
3711 RegRDX OpUse OpSet OpImplicit
3712 RegEAX OpUse OpSet OpImplicit
3713 Mdq_Operand OpUse OpSet
3714 NaClExpVector[10] = {
3715 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3716 { ExprRegister[0] , %rdx, ExprSet | ExprUsed | ExprSize64 },
3717 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3718 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
3719 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3720 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
3721 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3722 { ExprRegister[0] , %unknown, 0 },
3723 { ExprConstant[0] , 1, ExprSize8 },
3724 { ExprConstant[0] , 0, ExprSize8 },
3725 };
3726 0000000000000000: f0 48 0f c7 08 cmpxchg16b [%rax]
3727 0f c7 / 1 CMPXCHG16B OpcodeInModRm ModRmModIsnt0x3 OpcodeUse sModRm OpcodeLockable OperandSize_o
3728 Cmpxchg16b {%rdx}, {%eax}, $Mdq
3729 RegRDX OpUse OpSet OpImplicit
3730 RegEAX OpUse OpSet OpImplicit
3731 Mdq_Operand OpUse OpSet
3732 NaClExpVector[10] = {
3733 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3734 { ExprRegister[0] , %rdx, ExprSet | ExprUsed | ExprSize64 },
3735 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt | ExprImplicit },
3736 { ExprRegister[0] , %eax, ExprSet | ExprUsed | ExprSize32 },
3737 { OperandReference[1] , 2, ExprSize8 | ExprUnsignedInt },
3738 { ExprMemOffset[4] , 0, ExprSet | ExprUsed | ExprSize64 },
3739 { ExprRegister[0] , %rax, ExprUsed | ExprSize64 },
3740 { ExprRegister[0] , %unknown, 0 },
3741 { ExprConstant[0] , 1, ExprSize8 },
3742 { ExprConstant[0] , 0, ExprSize8 },
3743 };
3744 0000000000000000: 66 48 0f 7e c6 movq %rsi, %xmm0
3745 66 0f 7e SSE2 OpcodeUsesModRm OpcodeAllowsData16 SizeIgnore sData16 OperandSize_o
3746 Movq $Ed/q/q, $Vd/q/q
3747 E_Operand OpSet
3748 Xmm_G_Operand OpUse
3749 NaClExpVector[4] = {
3750 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3751 { ExprRegister[0] , %rsi, ExprSet | ExprSize64 },
3752 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3753 { ExprRegister[0] , %xmm0, ExprUsed },
3754 };
3755 0000000000000000: 48 0f 7e c6 movq %rsi, %mmx0
3756 0f 7e MMX OpcodeUsesModRm SizeIgnoresData16 OperandSize_ o
3757 Movq $Ed/q/q, $Pd/q/q
3758 E_Operand OpSet
3759 Mmx_G_Operand OpUse
3760 NaClExpVector[4] = {
3761 { OperandReference[1] , 0, ExprSize8 | ExprUnsignedInt },
3762 { ExprRegister[0] , %rsi, ExprSet | ExprSize64 },
3763 { OperandReference[1] , 1, ExprSize8 | ExprUnsignedInt },
3764 { ExprRegister[0] , %mmx0, ExprUsed },
3765 };
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