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| 1 /* | |
| 2 * Copyright (c) 2011 The Native Client Authors. All rights reserved. | |
| 3 * Use of this source code is governed by a BSD-style license that can be | |
| 4 * found in the LICENSE file. | |
| 5 */ | |
| 6 | |
| 7 /* | |
| 8 * Defines register layouts for x86 64 bit hardware registers for | |
| 9 * the use in modrm. | |
| 10 */ | |
| 11 | |
| 12 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_X86_NACL_REGS64_H_ | |
| 13 #define NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_X86_NACL_REGS64_H_ | |
| 14 | |
| 15 #include "native_client/src/trusted/validator/x86/decoder/ncopcode_desc.h" | |
| 16 | |
| 17 /* Define the number of general purpose registers defined for the given | |
| 18 * subarchitecture. | |
| 19 */ | |
| 20 #define NACL_REG_TABLE_SIZE_64 16 | |
| 21 | |
| 22 /* Defines that the nacl register is not defined. */ | |
| 23 #define NACL_REGISTER_UNDEFINED_64 (-1) | |
| 24 | |
| 25 /* Define the available 8-bit registers, for the given subarchitecture, | |
| 26 * assuming the REX prefix is not present. | |
| 27 * Note: The order is important, and is based on the indexing values used | |
| 28 * in the ModRm and SIB bytes (and the REX prefix if appropriate). | |
| 29 */ | |
| 30 static const NaClOpKind NaClRegTable8NoRex_64[NACL_REG_TABLE_SIZE_64] = { | |
| 31 RegAL, | |
| 32 RegCL, | |
| 33 RegDL, | |
| 34 RegBL, | |
| 35 RegAH, | |
| 36 RegCH, | |
| 37 RegDH, | |
| 38 RegBH, | |
| 39 RegUnknown, | |
| 40 RegUnknown, | |
| 41 RegUnknown, | |
| 42 RegUnknown, | |
| 43 RegUnknown, | |
| 44 RegUnknown, | |
| 45 RegUnknown, | |
| 46 RegUnknown | |
| 47 }; | |
| 48 | |
| 49 /* Define the available 8-bit registers, for the given subarchitecture, | |
| 50 * assuming the rex prefix is present. | |
| 51 * Note: The order is important, and is based on the indexing values used | |
| 52 * in the ModRm and SIB bytes (and the REX prefix if appropriate). | |
| 53 */ | |
| 54 static const NaClOpKind NaClRegTable8Rex_64[NACL_REG_TABLE_SIZE_64] = { | |
| 55 RegAL, | |
| 56 RegCL, | |
| 57 RegDL, | |
| 58 RegBL, | |
| 59 RegSPL, | |
| 60 RegBPL, | |
| 61 RegSIL, | |
| 62 RegDIL, | |
| 63 RegR8B, | |
| 64 RegR9B, | |
| 65 RegR10B, | |
| 66 RegR11B, | |
| 67 RegR12B, | |
| 68 RegR13B, | |
| 69 RegR14B, | |
| 70 RegR15B | |
| 71 }; | |
| 72 | |
| 73 /* Define the available 16-bit registers, for the given subarchitecture. | |
| 74 * Note: The order is important, and is based on the indexing values used | |
| 75 * in the ModRm and SIB bytes (and the REX prefix if appropriate). | |
| 76 */ | |
| 77 static const NaClOpKind NaClRegTable16_64[NACL_REG_TABLE_SIZE_64] = { | |
| 78 RegAX, | |
| 79 RegCX, | |
| 80 RegDX, | |
| 81 RegBX, | |
| 82 RegSP, | |
| 83 RegBP, | |
| 84 RegSI, | |
| 85 RegDI, | |
| 86 RegR8W, | |
| 87 RegR9W, | |
| 88 RegR10W, | |
| 89 RegR11W, | |
| 90 RegR12W, | |
| 91 RegR13W, | |
| 92 RegR14W, | |
| 93 RegR15W, | |
| 94 }; | |
| 95 | |
| 96 /* Define the available 32-bit registers, for the given subarchitecture. | |
| 97 * Note: The order is important, and is based on the indexing values used | |
| 98 * in the ModRm and SIB bytes (and the REX prefix if appropriate). | |
| 99 */ | |
| 100 static const NaClOpKind NaClRegTable32_64[NACL_REG_TABLE_SIZE_64] = { | |
| 101 RegEAX, | |
| 102 RegECX, | |
| 103 RegEDX, | |
| 104 RegEBX, | |
| 105 RegESP, | |
| 106 RegEBP, | |
| 107 RegESI, | |
| 108 RegEDI, | |
| 109 RegR8D, | |
| 110 RegR9D, | |
| 111 RegR10D, | |
| 112 RegR11D, | |
| 113 RegR12D, | |
| 114 RegR13D, | |
| 115 RegR14D, | |
| 116 RegR15D | |
| 117 }; | |
| 118 | |
| 119 /* Define the available 64-bit registers, for the given subarchitecture. | |
| 120 * Note: The order is important, and is based on the indexing values used | |
| 121 * in the ModRm and SIB bytes (and the REX prefix if appropriate). | |
| 122 */ | |
| 123 static const NaClOpKind NaClRegTable64_64[NACL_REG_TABLE_SIZE_64] = { | |
| 124 RegRAX, | |
| 125 RegRCX, | |
| 126 RegRDX, | |
| 127 RegRBX, | |
| 128 RegRSP, | |
| 129 RegRBP, | |
| 130 RegRSI, | |
| 131 RegRDI, | |
| 132 RegR8, | |
| 133 RegR9, | |
| 134 RegR10, | |
| 135 RegR11, | |
| 136 RegR12, | |
| 137 RegR13, | |
| 138 RegR14, | |
| 139 RegR15 | |
| 140 }; | |
| 141 | |
| 142 /* Define the available Mmx registers, for the given subarchitecture. | |
| 143 * Note: The order is important, and is based on the indexing values | |
| 144 * used in the ModRm and SIB bytes (and the REX prefix if appropriate). | |
| 145 */ | |
| 146 static const NaClOpKind NaClRegTableMmx_64[NACL_REG_TABLE_SIZE_64] = { | |
| 147 RegMMX0, | |
| 148 RegMMX1, | |
| 149 RegMMX2, | |
| 150 RegMMX3, | |
| 151 RegMMX4, | |
| 152 RegMMX5, | |
| 153 RegMMX6, | |
| 154 RegMMX7, | |
| 155 /* Intentionally repeat values, since Rex.B/R has no effect. */ | |
| 156 RegMMX0, | |
| 157 RegMMX1, | |
| 158 RegMMX2, | |
| 159 RegMMX3, | |
| 160 RegMMX4, | |
| 161 RegMMX5, | |
| 162 RegMMX6, | |
| 163 RegMMX7 | |
| 164 }; | |
| 165 | |
| 166 /* Define the available Xmm registers, for the given subarchitecture. | |
| 167 * Note: The order is important, and is based on the indexing values | |
| 168 * used in the ModRm and SIB bytes (and the REX prefix if appropriate). | |
| 169 */ | |
| 170 static const NaClOpKind NaClRegTableXmm_64[NACL_REG_TABLE_SIZE_64] = { | |
| 171 RegXMM0, | |
| 172 RegXMM1, | |
| 173 RegXMM2, | |
| 174 RegXMM3, | |
| 175 RegXMM4, | |
| 176 RegXMM5, | |
| 177 RegXMM6, | |
| 178 RegXMM7, | |
| 179 RegXMM8, | |
| 180 RegXMM9, | |
| 181 RegXMM10, | |
| 182 RegXMM11, | |
| 183 RegXMM12, | |
| 184 RegXMM13, | |
| 185 RegXMM14, | |
| 186 RegXMM15 | |
| 187 }; | |
| 188 | |
| 189 /* Defines the available control registers, for the given subarchitecture. | |
| 190 * Note: The order is important, and is based on the indexing values | |
| 191 * used in the ModRm byte (and the REX prefix if appropriate). | |
| 192 */ | |
| 193 static const NaClOpKind NaClRegTableC_64[NACL_REG_TABLE_SIZE_64] = { | |
| 194 RegCR0, | |
| 195 RegCR1, | |
| 196 RegCR2, | |
| 197 RegCR3, | |
| 198 RegCR4, | |
| 199 RegCR5, | |
| 200 RegCR6, | |
| 201 RegCR7, | |
| 202 RegCR8, | |
| 203 RegCR9, | |
| 204 RegCR10, | |
| 205 RegCR11, | |
| 206 RegCR12, | |
| 207 RegCR13, | |
| 208 RegCR14, | |
| 209 RegCR15, | |
| 210 }; | |
| 211 | |
| 212 /* Defines the available debug registers, for the given subarchitecture. | |
| 213 * Note: The order is important, and is based on the indexing values | |
| 214 * used in the ModRm byte (and the REX prefix if appropriate). | |
| 215 */ | |
| 216 static const NaClOpKind NaClRegTableD_64[NACL_REG_TABLE_SIZE_64] = { | |
| 217 RegDR0, | |
| 218 RegDR1, | |
| 219 RegDR2, | |
| 220 RegDR3, | |
| 221 RegDR4, | |
| 222 RegDR5, | |
| 223 RegDR6, | |
| 224 RegDR7, | |
| 225 RegDR8, | |
| 226 RegDR9, | |
| 227 RegDR10, | |
| 228 RegDR11, | |
| 229 RegDR12, | |
| 230 RegDR13, | |
| 231 RegDR14, | |
| 232 RegDR15, | |
| 233 }; | |
| 234 | |
| 235 #endif /* NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_X86_NACL_REGS64_H_ */ | |
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