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| 1 # Define set of possible instruction opcode flags that can apply | |
| 2 # to an instruction. These flags fully define how to parse an | |
| 3 # x86 instruction. Used by the decoder defined | |
| 4 # in native_client/src/trusted/validator/x86/decoder. | |
| 5 | |
| 6 # Note: The following sufficies are used: | |
| 7 # b - 8 bits. | |
| 8 # w - 16 bits. | |
| 9 # v - 32 bits. | |
| 10 # o - 64 bits. | |
| 11 | |
| 12 # Indicates the use of a rex pefix that affects the operand size or | |
| 13 # instruction semantics. Intel's Notation is REX.W. Only applies if | |
| 14 # decoder is running in 64-bit mode. | |
| 15 OpcodeUsesRexW | |
| 16 | |
| 17 # Indicates that opcode has REX prefix and REX.R is set. | |
| 18 OpcodeHasRexR | |
| 19 | |
| 20 # Defines instruction that uses opcode value 0-7 in the ModRm reg field | |
| 21 # as an operand. Intel's notation is /digit. Note: This data will be | |
| 22 # stored in the first operand, using a ModRmOpcode operand kind. | |
| 23 OpcodeInModRm | |
| 24 | |
| 25 # Defines a special 3DNOW 0F0F format instruction, which is used | |
| 26 # to parse all 3DNOW OFOF instructions, including the operands, | |
| 27 # and the trailing opcode in the immediate byte following the instruction. | |
| 28 Opcode0F0F | |
| 29 | |
| 30 # Defines instruction that uses opcode value 0-7 in the ModRm r/m field | |
| 31 # as an operand (in addition to the ModRm reg field). Note: These | |
| 32 # instructions also require the ModRm mod field to be 0x3. See | |
| 33 # section A.2.5 in the Intel manual (see ncdecode_tablegen.c for reference). | |
| 34 OpcodeInModRmRm | |
| 35 | |
| 36 # Defines an OpcodeInModRm, where the value of ModRm must also be less | |
| 37 # than 0xC0 (see x87 instructions for examples of this). | |
| 38 # NOTE: When this flag is set, so is OpcodeInModRm. | |
| 39 # NOTE: Also automatically added when an M_Operand is specified, so that | |
| 40 # none of the mod=0x3 registers are allowed. | |
| 41 OpcodeLtC0InModRm | |
| 42 | |
| 43 # Defines requirement during instruction matching that the ModRm mod field | |
| 44 # must be 0x3. | |
| 45 ModRmModIs0x3 | |
| 46 | |
| 47 # Defines requirement during instruction matching that the ModRm mod field | |
| 48 # must not be 0x3. | |
| 49 ModRmModIsnt0x3 | |
| 50 | |
| 51 # Defines requirement that the S_Operand value (modrm reg field) can only be | |
| 52 # 0..5. | |
| 53 ModRmRegSOperand | |
| 54 | |
| 55 # Defines instruction that the ModR/M byte contains a register operand and | |
| 56 # an r/m operand. Intel's notation is /r. | |
| 57 OpcodeUsesModRm | |
| 58 | |
| 59 # Defines the size of the immediate value that must follow the opcode. | |
| 60 # Intel's notation is ib, iw, id, and io. | |
| 61 OpcodeHasImmed | |
| 62 OpcodeHasImmed_b | |
| 63 OpcodeHasImmed_w | |
| 64 OpcodeHasImmed_v | |
| 65 OpcodeHasImmed_p # 6 bytes. | |
| 66 OpcodeHasImmed_o | |
| 67 OpcodeHasImmed_z # if effective size 2 bytes, 2 bytes. Otherwise 4 bytes. | |
| 68 | |
| 69 # Define the size of the second immediate value that must follow the first | |
| 70 # immediate opcode (if more than one immediate value). | |
| 71 OpcodeHasImmed2_b | |
| 72 OpcodeHasImmed2_w | |
| 73 OpcodeHasImmed2_v | |
| 74 | |
| 75 # Define the size of the immediate value that must follow the opcode, but | |
| 76 # uses the address size instead of the operand size. | |
| 77 OpcodeHasImmed_Addr | |
| 78 | |
| 79 # Defines a register code, from 0 through 7, added to the hexadecimal byte | |
| 80 # associated with the instruction, based on the operand size. | |
| 81 # Intel's notation is +rb. See Intel manual, table 3-1 for details. | |
| 82 # Note: to compute value 0-7, see first operand, which should be OperandBase. | |
| 83 OpcodePlusR | |
| 84 | |
| 85 # Defines a number used in floating-point instructions when one of the | |
| 86 # operands is ST(i) from the FPU register stack. The number i (which can | |
| 87 # range from 0 to 7) is added to the hexidecimal byte given at the left | |
| 88 # of the plus sign to form a single opcode byte. Intel's notation is +i. | |
| 89 # Note: to compute value 0-7, see first operand, which sould be OperandBase. | |
| 90 OpcodePlusI | |
| 91 | |
| 92 # Defines that in 64-bit mode, REX prefix should appear if using a 64-bit | |
| 93 # only register. Only applicable if running in 64-bit mode. | |
| 94 OpcodeRex | |
| 95 | |
| 96 # Indicates the REX prefix does not affect the legacy instruction in 64-bit | |
| 97 # mode. Intel's notation is N.P. | |
| 98 OpcodeLegacy | |
| 99 | |
| 100 # Defines that the opcode can be prefixed with a lock prefix. | |
| 101 OpcodeLockable | |
| 102 | |
| 103 # Defines that the opcode can be prefixed with a REP prefix. | |
| 104 OpcodeAllowsRep | |
| 105 | |
| 106 # Defines that the opcode can be prefixed with a REPNE prefix. | |
| 107 OpcodeAllowsRepne | |
| 108 | |
| 109 # Defines that the opcode can be prefixed with a DATA16 prefix. | |
| 110 OpcodeAllowsData16 | |
| 111 | |
| 112 # Defines that prefix 66 can't be used to define operand size. | |
| 113 # That is, only 32 or 64 bit values are allowed. | |
| 114 # Used for special cases where operand size is defined as "d/q". | |
| 115 # Also used to mark instructions with 66 prefix. | |
| 116 SizeIgnoresData16 | |
| 117 | |
| 118 # Defines the expected size of the operand. Can be repeated. | |
| 119 # The (possibly repeated) flags define the set possible operand | |
| 120 # sizes that are allowed by the opcode. | |
| 121 OperandSize_b | |
| 122 OperandSize_w | |
| 123 OperandSize_v | |
| 124 OperandSize_o | |
| 125 | |
| 126 # Defines the expected size of addresses. Can be repeated. | |
| 127 # The (possibly repeated) flags define the set of possible | |
| 128 # address sizes that are allowed by the opcode. | |
| 129 AddressSize_w | |
| 130 AddressSize_v | |
| 131 AddressSize_o | |
| 132 | |
| 133 # The instruction is not allowed by the Native Client Validator. | |
| 134 NaClIllegal | |
| 135 | |
| 136 # Operand size defaults to size 64 in 64-bit mode. | |
| 137 OperandSizeDefaultIs64 | |
| 138 | |
| 139 # Operand size must be 64 in 64-bit mode. | |
| 140 OperandSizeForce64 | |
| 141 | |
| 142 # The instruction requires that the CPUID sets bit 29 (long mode). | |
| 143 LongMode | |
| 144 | |
| 145 # Ignore multiple 66 prefices when counting the number of prefices allowed | |
| 146 # in NACL. | |
| 147 IgnorePrefixDATA16 | |
| 148 | |
| 149 # | |
| 150 #-------------------------------------------------------------- | |
| 151 # | |
| 152 # Note: instructions below this point are used elsewhere within native | |
| 153 # client, and do not effect the x86 instruction decoder. | |
| 154 | |
| 155 | |
| 156 # Opcode only applies if running in 32-bit mode. | |
| 157 # Used by the table generator to decide if the instruction | |
| 158 # should be included in the set of generated tables. | |
| 159 Opcode32Only | |
| 160 | |
| 161 # Opcode only applies if running in 64-bit mode. | |
| 162 # Used by the table generator to decide if the instruction | |
| 163 # should be included in the set of generated tables. | |
| 164 Opcode64Only | |
| 165 | |
| 166 # Mark instruction as (unconditional) jump. Used by the x86-64 | |
| 167 # validator to quickly categorize unconditional jumps. | |
| 168 JumpInstruction | |
| 169 | |
| 170 # Mark instruction as conditional jump. Used by the x86-64 | |
| 171 # validator to quickly categorize unconditional jumps. | |
| 172 ConditionalJump | |
| 173 | |
| 174 # Mark instruction as allowing branch hints 2e and 3e. | |
| 175 BranchHints | |
| 176 | |
| 177 # Mark the instruction as partial. This communicates to the print routines | |
| 178 # that the matched instruction is NOT a valid x86 instruction. Hence, it should | |
| 179 # use different print rules to better communicate what was partially matched. | |
| 180 PartialInstruction | |
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Chromium Code Reviews
Issue 625923004:
Delete old x86 validator. (Closed)
Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client