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| 1 /* | |
| 2 * Copyright (c) 2011 The Native Client Authors. All rights reserved. | |
| 3 * Use of this source code is governed by a BSD-style license that can be | |
| 4 * found in the LICENSE file. | |
| 5 */ | |
| 6 | |
| 7 /* | |
| 8 * Captures instructions that assumes the default size is 64 bits, | |
| 9 * instead of 32 bits. That is, effective operand size is 64 bits, | |
| 10 * even without a rex prefix. | |
| 11 * | |
| 12 * The tables below are from Table B-5 of Appendex B.4 in AMD document | |
| 13 * 24594-Rev.3.14-September 2007, "AMD64 Architecture Programmer's manual | |
| 14 * Volume 3: General-Purpose and System Instructions". | |
| 15 */ | |
| 16 | |
| 17 #ifndef NACL_TRUSTED_BUT_NOT_TCB | |
| 18 #error("This file is not meant for use in the TCB") | |
| 19 #endif | |
| 20 | |
| 21 #include "native_client/src/trusted/validator/x86/decoder/generator/defsize64.h" | |
| 22 | |
| 23 #include "native_client/src/include/nacl_macros.h" | |
| 24 #include "native_client/src/trusted/validator/x86/decoder/generator/ncdecode_for
ms.h" | |
| 25 #include "native_client/src/trusted/validator/x86/decoder/generator/ncdecode_tab
legen.h" | |
| 26 | |
| 27 /* List of instruction mnemonics that assumes the default size is 64 bits, | |
| 28 * and the mnemonic is sufficient to disambiguate the case. | |
| 29 */ | |
| 30 static const NaClMnemonic kNameSizeDefaultIs64[] = { | |
| 31 InstEnter, /* c8 */ | |
| 32 InstJo, /* 70, 0f 80 */ | |
| 33 InstJno, /* 71, 0f 81 */ | |
| 34 InstJb, /* 72, 0f 82 */ | |
| 35 InstJnb, /* 73, 0f 83 */ | |
| 36 InstJz, /* 74, 0f 84 */ | |
| 37 InstJnz, /* 75, 0f 85 */ | |
| 38 InstJbe, /* 76, 0f 86 */ | |
| 39 InstJnbe, /* 77, 0f 87 */ | |
| 40 InstJs, /* 78, 0f 88 */ | |
| 41 InstJns, /* 79, 0f 89 */ | |
| 42 InstJp, /* 7a, 0f 8a */ | |
| 43 InstJnp, /* 7b, 0f 8b */ | |
| 44 InstJl, /* 7c, 0f 8c */ | |
| 45 InstJnl, /* 7d, 0f 8d */ | |
| 46 InstJle, /* 7e, 0f 8e */ | |
| 47 InstJnle, /* 7f, 0f 8f */ | |
| 48 InstJcxz, /* e3 */ | |
| 49 InstJecxz, /* e3 */ | |
| 50 InstJrcxz, /* e3 */ | |
| 51 InstLeave, /* c9 */ | |
| 52 InstLoop, /* e2 */ | |
| 53 InstLoopne, /* e0 */ | |
| 54 InstLoope, /* e1 */ | |
| 55 /* | |
| 56 InstMovmskpd, ** 66 0f 50 - Intel(tm) claims 64-bit size assumption, | |
| 57 * while AMD does not. If we go ahead and assume that | |
| 58 * all 64-bits can be effected, we do not break anything. | |
| 59 * Hence, we generalize to 64-bit default. | |
| 60 */ | |
| 61 InstPopf, /* 9d */ | |
| 62 InstPopfd, /* 9d */ | |
| 63 InstPopfq, /* 9d */ | |
| 64 InstPushf, /* 9c */ | |
| 65 InstPushfd, /* 9c */ | |
| 66 InstPushfq /* 9c */ | |
| 67 | |
| 68 }; | |
| 69 | |
| 70 static const NaClNameOpcodeSeq kNameSeqSizeDefaultIs64[] = { | |
| 71 { InstCall , { 0xe8 , END_OPCODE_SEQ } }, | |
| 72 { InstCall , { 0xff , SL(2) , END_OPCODE_SEQ } }, | |
| 73 { InstJmp , { 0xe9 , END_OPCODE_SEQ } }, | |
| 74 { InstJmp , { 0xeb , END_OPCODE_SEQ } }, | |
| 75 { InstJmp , { 0xff , SL(4) , END_OPCODE_SEQ } }, | |
| 76 { InstPop , { 0x58 , END_OPCODE_SEQ } }, | |
| 77 { InstPop , { 0x59 , END_OPCODE_SEQ } }, | |
| 78 { InstPop , { 0x5a , END_OPCODE_SEQ } }, | |
| 79 { InstPop , { 0x5b , END_OPCODE_SEQ } }, | |
| 80 { InstPop , { 0x5c , END_OPCODE_SEQ } }, | |
| 81 { InstPop , { 0x5d , END_OPCODE_SEQ } }, | |
| 82 { InstPop , { 0x5e , END_OPCODE_SEQ } }, | |
| 83 { InstPop , { 0x5f , END_OPCODE_SEQ } }, | |
| 84 { InstPop , { 0x8f , SL(0) , END_OPCODE_SEQ } }, | |
| 85 { InstPop , { 0x0f , 0xa1 , END_OPCODE_SEQ } } , | |
| 86 { InstPop , { 0x0f , 0xa9 , END_OPCODE_SEQ } }, | |
| 87 { InstPush , { 0x50 , END_OPCODE_SEQ } }, | |
| 88 { InstPush , { 0x51 , END_OPCODE_SEQ } }, | |
| 89 { InstPush , { 0x52 , END_OPCODE_SEQ } }, | |
| 90 { InstPush , { 0x53 , END_OPCODE_SEQ } }, | |
| 91 { InstPush , { 0x54 , END_OPCODE_SEQ } }, | |
| 92 { InstPush , { 0x55 , END_OPCODE_SEQ } }, | |
| 93 { InstPush , { 0x56 , END_OPCODE_SEQ } }, | |
| 94 { InstPush , { 0x57 , END_OPCODE_SEQ } }, | |
| 95 { InstPush , { 0x6a , END_OPCODE_SEQ } }, | |
| 96 { InstPush , { 0x68 , END_OPCODE_SEQ } }, | |
| 97 { InstPush , { 0xff , SL(6) , END_OPCODE_SEQ } }, | |
| 98 { InstPush , { 0x0f , 0xa0 , END_OPCODE_SEQ } }, | |
| 99 { InstPush , { 0x0f , 0xa8 , END_OPCODE_SEQ } }, | |
| 100 { InstRet , { 0xc2 , END_OPCODE_SEQ } }, | |
| 101 { InstRet , { 0xc3 , END_OPCODE_SEQ } }, | |
| 102 }; | |
| 103 | |
| 104 void NaClAddSizeDefaultIs64(void) { | |
| 105 NaClModeledInst* inst = NaClGetDefInst(); | |
| 106 if ((X86_64 == NACL_FLAGS_run_mode) && | |
| 107 (NaClOperandSizes(inst) & NACL_IFLAG(OperandSize_o)) && | |
| 108 NaClInInstructionSet(kNameSizeDefaultIs64, | |
| 109 NACL_ARRAY_SIZE(kNameSizeDefaultIs64), | |
| 110 kNameSeqSizeDefaultIs64, | |
| 111 NACL_ARRAY_SIZE(kNameSeqSizeDefaultIs64))) { | |
| 112 NaClAddIFlags(NACL_IFLAG(OperandSizeDefaultIs64)); | |
| 113 } | |
| 114 } | |
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