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| 1 //===- subzero/src/IceRegAlloc.cpp - Linear-scan implementation -----------===// | 1 //===- subzero/src/IceRegAlloc.cpp - Linear-scan implementation -----------===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 // | 9 // |
| 10 // This file implements the LinearScan class, which performs the | 10 // This file implements the LinearScan class, which performs the |
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| 61 // cases. | 61 // cases. |
| 62 // | 62 // |
| 63 // Requires running Cfg::liveness(Liveness_Intervals) in | 63 // Requires running Cfg::liveness(Liveness_Intervals) in |
| 64 // preparation. Results are assigned to Variable::RegNum for each | 64 // preparation. Results are assigned to Variable::RegNum for each |
| 65 // Variable. | 65 // Variable. |
| 66 void LinearScan::scan(const llvm::SmallBitVector &RegMaskFull) { | 66 void LinearScan::scan(const llvm::SmallBitVector &RegMaskFull) { |
| 67 static TimerIdT IDscan = GlobalContext::getTimerID("linearScan"); | 67 static TimerIdT IDscan = GlobalContext::getTimerID("linearScan"); |
| 68 TimerMarker T(IDscan, Func->getContext()); | 68 TimerMarker T(IDscan, Func->getContext()); |
| 69 assert(RegMaskFull.any()); // Sanity check | 69 assert(RegMaskFull.any()); // Sanity check |
| 70 Unhandled.clear(); | 70 Unhandled.clear(); |
| 71 UnhandledPrecolored.clear(); | |
| 71 Handled.clear(); | 72 Handled.clear(); |
| 72 Inactive.clear(); | 73 Inactive.clear(); |
| 73 Active.clear(); | 74 Active.clear(); |
| 74 Ostream &Str = Func->getContext()->getStrDump(); | 75 Ostream &Str = Func->getContext()->getStrDump(); |
| 75 bool Verbose = Func->getContext()->isVerbose(IceV_LinearScan); | 76 bool Verbose = Func->getContext()->isVerbose(IceV_LinearScan); |
| 76 Func->resetCurrentNode(); | 77 Func->resetCurrentNode(); |
| 77 VariablesMetadata *VMetadata = Func->getVMetadata(); | 78 VariablesMetadata *VMetadata = Func->getVMetadata(); |
| 78 | 79 |
| 79 // Gather the live ranges of all variables and add them to the | 80 // Gather the live ranges of all variables and add them to the |
| 80 // Unhandled set. TODO: Unhandled is a set<> which is based on a | 81 // Unhandled set. TODO: Unhandled is a set<> which is based on a |
| 81 // balanced binary tree, so inserting live ranges for N variables is | 82 // balanced binary tree, so inserting live ranges for N variables is |
| 82 // O(N log N) complexity. N may be proportional to the number of | 83 // O(N log N) complexity. N may be proportional to the number of |
| 83 // instructions, thanks to temporary generation during lowering. As | 84 // instructions, thanks to temporary generation during lowering. As |
| 84 // a result, it may be useful to design a better data structure for | 85 // a result, it may be useful to design a better data structure for |
| 85 // storing Func->getVariables(). | 86 // storing Func->getVariables(). |
| 86 const VarList &Vars = Func->getVariables(); | 87 const VarList &Vars = Func->getVariables(); |
| 87 { | 88 { |
| 88 static TimerIdT IDinitUnhandled = | 89 static TimerIdT IDinitUnhandled = |
| 89 GlobalContext::getTimerID("initUnhandled"); | 90 GlobalContext::getTimerID("initUnhandled"); |
| 90 TimerMarker T(IDinitUnhandled, Func->getContext()); | 91 TimerMarker T(IDinitUnhandled, Func->getContext()); |
| 91 for (Variable *Var : Vars) { | 92 for (Variable *Var : Vars) { |
| 92 // Explicitly don't consider zero-weight variables, which are | 93 // Explicitly don't consider zero-weight variables, which are |
| 93 // meant to be spill slots. | 94 // meant to be spill slots. |
| 94 if (Var->getWeight() == RegWeight::Zero) | 95 if (Var->getWeight() == RegWeight::Zero) |
| 95 continue; | 96 continue; |
| 96 // Don't bother if the variable has a null live range, which means | 97 // Don't bother if the variable has a null live range, which means |
| 97 // it was never referenced. | 98 // it was never referenced. |
| 98 if (Var->getLiveRange().isEmpty()) | 99 if (Var->getLiveRange().isEmpty()) |
| 99 continue; | 100 continue; |
|
jvoung (off chromium)
2014/10/02 16:08:18
Tiny nit: I don't know if it saves anything to mak
jvoung (off chromium)
2014/10/02 17:00:06
Ah maybe not -- there's probably something with mo
Jim Stichnoth
2014/10/02 19:41:47
Done. Probably doesn't affect performance, but it
Jim Stichnoth
2014/10/02 19:41:47
Well, I still like it better your way. :)
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| 100 Unhandled.insert(LiveRangeWrapper(Var)); | 101 Unhandled.insert(LiveRangeWrapper(Var)); |
| 101 if (Var->hasReg()) { | 102 if (Var->hasReg()) { |
| 102 Var->setRegNumTmp(Var->getRegNum()); | 103 Var->setRegNumTmp(Var->getRegNum()); |
| 103 Var->setLiveRangeInfiniteWeight(); | 104 Var->setLiveRangeInfiniteWeight(); |
| 105 UnhandledPrecolored.insert(LiveRangeWrapper(Var)); | |
| 104 } | 106 } |
| 105 } | 107 } |
| 106 } | 108 } |
| 107 | 109 |
| 108 // RegUses[I] is the number of live ranges (variables) that register | 110 // RegUses[I] is the number of live ranges (variables) that register |
| 109 // I is currently assigned to. It can be greater than 1 as a result | 111 // I is currently assigned to. It can be greater than 1 as a result |
| 110 // of AllowOverlap inference below. | 112 // of AllowOverlap inference below. |
| 111 std::vector<int> RegUses(RegMaskFull.size()); | 113 std::vector<int> RegUses(RegMaskFull.size()); |
| 112 // Unhandled is already set to all ranges in increasing order of | 114 // Unhandled is already set to all ranges in increasing order of |
| 113 // start points. | 115 // start points. |
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| 138 // RegNumTmp should have already been set above. | 140 // RegNumTmp should have already been set above. |
| 139 assert(Cur.Var->getRegNumTmp() == RegNum); | 141 assert(Cur.Var->getRegNumTmp() == RegNum); |
| 140 if (Verbose) { | 142 if (Verbose) { |
| 141 Str << "Precoloring "; | 143 Str << "Precoloring "; |
| 142 Cur.dump(Func); | 144 Cur.dump(Func); |
| 143 Str << "\n"; | 145 Str << "\n"; |
| 144 } | 146 } |
| 145 Active.push_back(Cur); | 147 Active.push_back(Cur); |
| 146 assert(RegUses[RegNum] >= 0); | 148 assert(RegUses[RegNum] >= 0); |
| 147 ++RegUses[RegNum]; | 149 ++RegUses[RegNum]; |
| 150 assert(!UnhandledPrecolored.empty()); | |
| 151 assert(UnhandledPrecolored.begin()->Var == Cur.Var); | |
| 152 UnhandledPrecolored.erase(UnhandledPrecolored.begin()); | |
| 148 continue; | 153 continue; |
| 149 } | 154 } |
| 150 | 155 |
| 151 // Check for active ranges that have expired or become inactive. | 156 // Check for active ranges that have expired or become inactive. |
| 152 for (auto I = Active.begin(), E = Active.end(); I != E; I = Next) { | 157 for (auto I = Active.begin(), E = Active.end(); I != E; I = Next) { |
| 153 Next = I; | 158 Next = I; |
| 154 ++Next; | 159 ++Next; |
| 155 LiveRangeWrapper Item = *I; | 160 LiveRangeWrapper Item = *I; |
| 156 bool Moved = false; | 161 bool Moved = false; |
| 157 if (Item.endsBefore(Cur)) { | 162 if (Item.endsBefore(Cur)) { |
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| 303 overlapsDefs(Func, Cur, Item.Var)) { | 308 overlapsDefs(Func, Cur, Item.Var)) { |
| 304 AllowOverlap = false; | 309 AllowOverlap = false; |
| 305 dumpDisableOverlap(Func, Item.Var, "Active"); | 310 dumpDisableOverlap(Func, Item.Var, "Active"); |
| 306 } | 311 } |
| 307 } | 312 } |
| 308 | 313 |
| 309 // Remove registers from the Free[] list where an Unhandled range | 314 // Remove registers from the Free[] list where an Unhandled range |
| 310 // overlaps with the current range and is precolored. | 315 // overlaps with the current range and is precolored. |
| 311 // Cur.endsBefore(Item) is an early exit check that turns a | 316 // Cur.endsBefore(Item) is an early exit check that turns a |
| 312 // guaranteed O(N^2) algorithm into expected linear complexity. | 317 // guaranteed O(N^2) algorithm into expected linear complexity. |
| 313 llvm::SmallBitVector PrecoloredUnhandled(RegMask.size()); | 318 llvm::SmallBitVector PrecoloredUnhandledMask(RegMask.size()); |
| 314 // Note: PrecoloredUnhandled is only used for dumping. | 319 // Note: PrecoloredUnhandledMask is only used for dumping. |
| 315 for (const LiveRangeWrapper &Item : Unhandled) { | 320 for (const LiveRangeWrapper &Item : UnhandledPrecolored) { |
| 321 assert(Item.Var->hasReg()); | |
| 316 if (Cur.endsBefore(Item)) | 322 if (Cur.endsBefore(Item)) |
| 317 break; | 323 break; |
| 318 if (Item.Var->hasReg() && Item.overlaps(Cur)) { | 324 if (Item.overlaps(Cur)) { |
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jvoung (off chromium)
2014/10/02 16:08:18
Any idea if overlaps() is more expensive, or check
Jim Stichnoth
2014/10/02 19:41:47
I don't think that would be worth it:
1. After co
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| 319 int32_t ItemReg = Item.Var->getRegNum(); // Note: not getRegNumTmp() | 325 int32_t ItemReg = Item.Var->getRegNum(); // Note: not getRegNumTmp() |
| 320 Free[ItemReg] = false; | 326 Free[ItemReg] = false; |
| 321 PrecoloredUnhandled[ItemReg] = true; | 327 PrecoloredUnhandledMask[ItemReg] = true; |
| 322 // Disable AllowOverlap if the preferred register is one of | 328 // Disable AllowOverlap if the preferred register is one of |
| 323 // these precolored unhandled overlapping ranges. | 329 // these precolored unhandled overlapping ranges. |
| 324 if (AllowOverlap && ItemReg == PreferReg) { | 330 if (AllowOverlap && ItemReg == PreferReg) { |
| 325 AllowOverlap = false; | 331 AllowOverlap = false; |
| 326 dumpDisableOverlap(Func, Item.Var, "PrecoloredUnhandled"); | 332 dumpDisableOverlap(Func, Item.Var, "PrecoloredUnhandled"); |
| 327 } | 333 } |
| 328 } | 334 } |
| 329 } | 335 } |
| 330 | 336 |
| 331 // Print info about physical register availability. | 337 // Print info about physical register availability. |
| 332 if (Verbose) { | 338 if (Verbose) { |
| 333 for (SizeT i = 0; i < RegMask.size(); ++i) { | 339 for (SizeT i = 0; i < RegMask.size(); ++i) { |
| 334 if (RegMask[i]) { | 340 if (RegMask[i]) { |
| 335 Str << Func->getTarget()->getRegName(i, IceType_i32) | 341 Str << Func->getTarget()->getRegName(i, IceType_i32) |
| 336 << "(U=" << RegUses[i] << ",F=" << Free[i] | 342 << "(U=" << RegUses[i] << ",F=" << Free[i] |
| 337 << ",P=" << PrecoloredUnhandled[i] << ") "; | 343 << ",P=" << PrecoloredUnhandledMask[i] << ") "; |
| 338 } | 344 } |
| 339 } | 345 } |
| 340 Str << "\n"; | 346 Str << "\n"; |
| 341 } | 347 } |
| 342 | 348 |
| 343 if (Prefer && (AllowOverlap || Free[PreferReg])) { | 349 if (Prefer && (AllowOverlap || Free[PreferReg])) { |
| 344 // First choice: a preferred register that is either free or is | 350 // First choice: a preferred register that is either free or is |
| 345 // allowed to overlap with its linked variable. | 351 // allowed to overlap with its linked variable. |
| 346 Cur.Var->setRegNumTmp(PreferReg); | 352 Cur.Var->setRegNumTmp(PreferReg); |
| 347 if (Verbose) { | 353 if (Verbose) { |
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| 378 Weights[RegNum].addWeight(Item.range().getWeight()); | 384 Weights[RegNum].addWeight(Item.range().getWeight()); |
| 379 } | 385 } |
| 380 // Same as above, but check Inactive ranges instead of Active. | 386 // Same as above, but check Inactive ranges instead of Active. |
| 381 for (const LiveRangeWrapper &Item : Inactive) { | 387 for (const LiveRangeWrapper &Item : Inactive) { |
| 382 int32_t RegNum = Item.Var->getRegNumTmp(); | 388 int32_t RegNum = Item.Var->getRegNumTmp(); |
| 383 assert(Item.Var->hasRegTmp()); | 389 assert(Item.Var->hasRegTmp()); |
| 384 if (Item.overlaps(Cur)) | 390 if (Item.overlaps(Cur)) |
| 385 Weights[RegNum].addWeight(Item.range().getWeight()); | 391 Weights[RegNum].addWeight(Item.range().getWeight()); |
| 386 } | 392 } |
| 387 // Check Unhandled ranges that overlap Cur and are precolored. | 393 // Check Unhandled ranges that overlap Cur and are precolored. |
| 388 // Cur.endsBefore(*I) is an early exit check that turns a | 394 // Cur.endsBefore(Item) is an early exit check that turns a |
| 389 // guaranteed O(N^2) algorithm into expected linear complexity. | 395 // guaranteed O(N^2) algorithm into expected linear complexity. |
| 390 for (const LiveRangeWrapper &Item : Unhandled) { | 396 for (const LiveRangeWrapper &Item : UnhandledPrecolored) { |
| 397 assert(Item.Var->hasReg()); | |
| 391 if (Cur.endsBefore(Item)) | 398 if (Cur.endsBefore(Item)) |
| 392 break; | 399 break; |
| 393 int32_t RegNum = Item.Var->getRegNumTmp(); | 400 if (Item.overlaps(Cur)) { |
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jvoung (off chromium)
2014/10/02 16:08:18
Does this loop find the same set of Items which ov
Jim Stichnoth
2014/10/02 19:41:47
Nice! We can pull Weights[] earlier in the loop a
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| 394 if (RegNum < 0) | 401 int32_t RegNum = Item.Var->getRegNumTmp(); |
| 395 continue; | |
| 396 if (Item.overlaps(Cur)) | |
| 397 Weights[RegNum].setWeight(RegWeight::Inf); | 402 Weights[RegNum].setWeight(RegWeight::Inf); |
| 403 } | |
| 398 } | 404 } |
| 399 | 405 |
| 400 // All the weights are now calculated. Find the register with | 406 // All the weights are now calculated. Find the register with |
| 401 // smallest weight. | 407 // smallest weight. |
| 402 int32_t MinWeightIndex = RegMask.find_first(); | 408 int32_t MinWeightIndex = RegMask.find_first(); |
| 403 // MinWeightIndex must be valid because of the initial | 409 // MinWeightIndex must be valid because of the initial |
| 404 // RegMask.any() test. | 410 // RegMask.any() test. |
| 405 assert(MinWeightIndex >= 0); | 411 assert(MinWeightIndex >= 0); |
| 406 for (SizeT i = MinWeightIndex + 1; i < Weights.size(); ++i) { | 412 for (SizeT i = MinWeightIndex + 1; i < Weights.size(); ++i) { |
| 407 if (RegMask[i] && Weights[i] < Weights[MinWeightIndex]) | 413 if (RegMask[i] && Weights[i] < Weights[MinWeightIndex]) |
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| 551 Str << "\n"; | 557 Str << "\n"; |
| 552 } | 558 } |
| 553 Str << "++++++ Inactive:\n"; | 559 Str << "++++++ Inactive:\n"; |
| 554 for (const LiveRangeWrapper &Item : Inactive) { | 560 for (const LiveRangeWrapper &Item : Inactive) { |
| 555 Item.dump(Func); | 561 Item.dump(Func); |
| 556 Str << "\n"; | 562 Str << "\n"; |
| 557 } | 563 } |
| 558 } | 564 } |
| 559 | 565 |
| 560 } // end of namespace Ice | 566 } // end of namespace Ice |
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