Handle GPR and vector shift ops. Handle pmull also.

tests_lit/llvm2ice_tests/vector-arith.ll

Index: tests_lit/llvm2ice_tests/vector-arith.ll
diff --git a/tests_lit/llvm2ice_tests/vector-arith.ll b/tests_lit/llvm2ice_tests/vector-arith.ll
index 29bb57fedffbf3700951bdcf59df02d85d42d91d..dfa4462f6aaa921db68579336448db44e238b217 100644
--- a/tests_lit/llvm2ice_tests/vector-arith.ll
+++ b/tests_lit/llvm2ice_tests/vector-arith.ll
@@ -21,7 +21,6 @@
 ; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
 ; RUN:   | FileCheck --check-prefix=SSE41 %s
 ; RUN: %p2i -i %s -a --verbose none | FileCheck --check-prefix=ERRORS %s
-; RUN: %p2i -i %s --insts | %szdiff %s | FileCheck --check-prefix=DUMP %s
 
 define <4 x float> @test_fadd(<4 x float> %arg0, <4 x float> %arg1) {
 entry:
@@ -343,6 +342,16 @@ entry:
 ; CHECK: pmullw
 }
 
+define <8 x i16> @test_mul_v8i16_mem(<8 x i16> %arg0, i32 %arg1_iptr) {
+entry:

[jvoung (off chromium), 2014/10/03 18:17:20]

I moved this over to the address-mode-opt tests, which only tests O2.

+  %arg1_ptr = inttoptr i32 %arg1_iptr to <8 x i16>*
+  %arg1 = load <8 x i16>* %arg1_ptr, align 2
+  %res_vec = mul <8 x i16> %arg0, %arg1
+  ret <8 x i16> %res_vec
+; CHECK-LABEL: test_mul_v8i16_mem:
+; CHECK: pmullw xmm{{.*}}, xmmword ptr
+}
+
 define <8 x i16> @test_shl_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
 entry:
   %res = shl <8 x i16> %arg0, %arg1
@@ -500,6 +509,20 @@ entry:
 ; SSE41: pmulld
 }
 
+define <4 x i32> @test_mul_v4i32_mem(<4 x i32> %arg0, i32 %arg1_iptr) {
+entry:
+  %arg1_ptr = inttoptr i32 %arg1_iptr to <4 x i32>*
+  %arg1 = load <4 x i32>* %arg1_ptr, align 4
+  %res = mul <4 x i32> %arg0, %arg1
+  ret <4 x i32> %res
+; CHECK-LABEL: test_mul_v4i32_mem:
+; CHECK: pmuludq xmm{{.*}}, xmmword ptr
+; CHECK: pmuludq
+;
+; SSE41-LABEL: test_mul_v4i32_mem:
+; SSE41: pmulld xmm{{.*}}, xmmword ptr
+}
+
 define <4 x i32> @test_shl_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
 entry:
   %res = shl <4 x i32> %arg0, %arg1