Handle GPR and vector shift ops. Handle pmull also.

tests_lit/llvm2ice_tests/vector-arith.ll

 ; This test checks support for vector arithmetic.
 
 ; TODO(jvoung): fix extra "CALLTARGETS" run. The llvm-objdump symbolizer
 ; doesn't know how to symbolize non-section-local functions.
 ; The newer LLVM 3.6 one does work, but watch out for other bugs.
 
 ; RUN: %p2i -i %s -a -O2 --verbose none\
 ; RUN:   | FileCheck --check-prefix=CALLTARGETS %s
 ; RUN: %p2i -i %s -a -O2 --verbose none \
 ; RUN:   | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
 ; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
 ; RUN: %p2i -i %s -a -Om1 --verbose none \
 ; RUN:   | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
 ; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
 ; RUN: %p2i -i %s -a -O2 -mattr=sse4.1 --verbose none \
 ; RUN:   | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
 ; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
 ; RUN:   | FileCheck --check-prefix=SSE41 %s
 ; RUN: %p2i -i %s -a -Om1 -mattr=sse4.1 --verbose none \
 ; RUN:   | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
 ; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
 ; RUN:   | FileCheck --check-prefix=SSE41 %s
 ; RUN: %p2i -i %s -a --verbose none | FileCheck --check-prefix=ERRORS %s
-; RUN: %p2i -i %s --insts | %szdiff %s | FileCheck --check-prefix=DUMP %s

[jvoung (off chromium), 2014/10/02 22:04:13]

Hmm p2i leaves out the inttoptr, so I wasn't sure how to work around that.

[Jim Stichnoth, 2014/10/03 04:00:00]

Yeah, the DUMP test's days are numbered, as we move over to the direct bitcode
reader.

 
 define <4 x float> @test_fadd(<4 x float> %arg0, <4 x float> %arg1) {
 entry:
   %res = fadd <4 x float> %arg0, %arg1
   ret <4 x float> %res
 ; CHECK-LABEL: test_fadd:
 ; CHECK: addps
 }
 
 define <4 x float> @test_fsub(<4 x float> %arg0, <4 x float> %arg1) {
@@ skipping 301 matching lines @@
 }
 
 define <8 x i16> @test_mul_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
 entry:
   %res = mul <8 x i16> %arg0, %arg1
   ret <8 x i16> %res
 ; CHECK-LABEL: test_mul_v8i16:
 ; CHECK: pmullw
 }
 
+define <8 x i16> @test_mul_v8i16_mem(<8 x i16> %arg0, i32 %arg1_iptr) {
+entry:
+  %arg1_ptr = inttoptr i32 %arg1_iptr to <8 x i16>*
+  %arg1 = load <8 x i16>* %arg1_ptr, align 2
+  %res_vec = mul <8 x i16> %arg0, %arg1
+  ret <8 x i16> %res_vec
+; CHECK-LABEL: test_mul_v8i16_mem:
+; CHECK: pmullw xmm{{.*}}, xmmword ptr
+}
+
 define <8 x i16> @test_shl_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
 entry:
   %res = shl <8 x i16> %arg0, %arg1
   ret <8 x i16> %res
 ; CHECK-LABEL: test_shl_v8i16:
 ; CHECK: shl
 ; CHECK: shl
 ; CHECK: shl
 ; CHECK: shl
 ; CHECK: shl
@@ skipping 137 matching lines @@
   %res = mul <4 x i32> %arg0, %arg1
   ret <4 x i32> %res
 ; CHECK-LABEL: test_mul_v4i32:
 ; CHECK: pmuludq
 ; CHECK: pmuludq
 ;
 ; SSE41-LABEL: test_mul_v4i32:
 ; SSE41: pmulld
 }
 
+define <4 x i32> @test_mul_v4i32_mem(<4 x i32> %arg0, i32 %arg1_iptr) {
+entry:
+  %arg1_ptr = inttoptr i32 %arg1_iptr to <4 x i32>*
+  %arg1 = load <4 x i32>* %arg1_ptr, align 4
+  %res = mul <4 x i32> %arg0, %arg1
+  ret <4 x i32> %res
+; CHECK-LABEL: test_mul_v4i32_mem:
+; CHECK: pmuludq xmm{{.*}}, xmmword ptr
+; CHECK: pmuludq
+;
+; SSE41-LABEL: test_mul_v4i32_mem:
+; SSE41: pmulld xmm{{.*}}, xmmword ptr
+}
+
 define <4 x i32> @test_shl_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
 entry:
   %res = shl <4 x i32> %arg0, %arg1
   ret <4 x i32> %res
 ; CHECK-LABEL: test_shl_v4i32:
 ; CHECK: shl
 ; CHECK: shl
 ; CHECK: shl
 ; CHECK: shl
 
@@ skipping 62 matching lines @@
   ret <4 x i32> %res
 ; CHECK-LABEL: test_srem_v4i32:
 ; CHECK: idiv
 ; CHECK: idiv
 ; CHECK: idiv
 ; CHECK: idiv
 }
 
 ; ERRORS-NOT: ICE translation error
 ; DUMP-NOT: SZ