Handle GPR and vector shift ops. Handle pmull also.

tests_lit/assembler/x86/immediate_encodings.ll

 ; Tests various aspects of x86 immediate encoding. Some encodings are shorter.
 ; For example, the encoding is shorter for 8-bit immediates or when using EAX.
 ; This assumes that EAX is chosen as the first free register in O2 mode.
 
 ; RUN: %p2i -i %s --args -O2 --verbose none \
 ; RUN:   | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
 ; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
 ; RUN: %p2i -i %s --args --verbose none | FileCheck --check-prefix=ERRORS %s
 ; RUN: %p2i -i %s --insts | %szdiff %s | FileCheck --check-prefix=DUMP %s
 
@@ skipping 236 matching lines @@
 ; CHECK: 69 c0 00 04 00 00  imul eax, eax, 1024
 
 define internal i32 @testMul32Imm16Neg(i32 %arg) {
 entry:
   %result = mul i32 %arg, -256
   ret i32 %result
 }
 ; CHECK-LABEL: testMul32Imm16Neg
 ; CHECK: 69 c0 00 ff ff ff  imul eax, eax, 4294967040
 
+; The GPR shift instructions either allow an 8-bit immediate or
+; have a special encoding for "1".
+define internal i32 @testShl16Imm8(i32 %arg) {
+entry:
+  %arg_i16 = trunc i32 %arg to i16
+  %tmp = shl i16 %arg_i16, 13
+  %result = zext i16 %tmp to i32
+  ret i32 %result
+}
+; CHECK-LABEL: testShl16Imm8
+; CHECK: 66 c1 e0 0d shl ax, 13
+
+define internal i32 @testShl16Imm1(i32 %arg) {
+entry:
+  %arg_i16 = trunc i32 %arg to i16
+  %tmp = shl i16 %arg_i16, 1
+  %result = zext i16 %tmp to i32
+  ret i32 %result
+}
+; CHECK-LABEL: testShl16Imm1
+; CHECK: 66 d1 e0 shl ax
+
 ; ERRORS-NOT: ICE translation error
 ; DUMP-NOT: SZ