Handle GPR and vector shift ops. Handle pmull also.

src/IceInstX8632.cpp

 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the InstX8632 and OperandX8632 classes,
@@ skipping 518 matching lines @@
   } else if (const ConstantInteger32 *Imm =
                  llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.GPRImm))(Ty, VarReg, x86::Immediate(Imm->getValue()));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
   Ostream &Str = Func->getContext()->getStrEmit();
   emitIASBytes(Str, Asm, StartPosition);
 }
 
+void emitIASGPRShift(const Cfg *Func, Type Ty, const Variable *Var,
+                     const Operand *Src,
+                     const x86::AssemblerX86::GPREmitterShiftOp &Emitter) {
+  x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
+  intptr_t StartPosition = Asm->GetPosition();
+  // Technically, the Dest Var can be mem as well, but we only use Reg.
+  // We can extend this to check Dest if we decide to use that form.
+  assert(Var->hasReg());
+  // We cheat a little and use GPRRegister even for byte operations.
+  RegX8632::GPRRegister VarReg =
+      RegX8632::getEncodedByteRegOrGPR(Ty, Var->getRegNum());
+  // Src must be reg == ECX or an Imm8.
+  // This is asserted by the assembler.
+  if (const Variable *SrcVar = llvm::dyn_cast<Variable>(Src)) {
+    assert(SrcVar->hasReg());
+    RegX8632::GPRRegister SrcReg =
+        RegX8632::getEncodedByteRegOrGPR(Ty, SrcVar->getRegNum());
+    (Asm->*(Emitter.GPRGPR))(Ty, VarReg, SrcReg);
+  } else if (const ConstantInteger32 *Imm =
+                 llvm::dyn_cast<ConstantInteger32>(Src)) {
+    (Asm->*(Emitter.GPRImm))(Ty, VarReg, x86::Immediate(Imm->getValue()));
+  } else {
+    llvm_unreachable("Unexpected operand type");
+  }
+  Ostream &Str = Func->getContext()->getStrEmit();
+  emitIASBytes(Str, Asm, StartPosition);
+}
+
+void emitIASXmmShift(const Cfg *Func, Type Ty, const Variable *Var,
+                     const Operand *Src,
+                     const x86::AssemblerX86::XmmEmitterShiftOp &Emitter) {
+  x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
+  intptr_t StartPosition = Asm->GetPosition();
+  assert(Var->hasReg());
+  RegX8632::XmmRegister VarReg = RegX8632::getEncodedXmm(Var->getRegNum());
+  if (const Variable *SrcVar = llvm::dyn_cast<Variable>(Src)) {
+    if (SrcVar->hasReg()) {
+      RegX8632::XmmRegister SrcReg =
+          RegX8632::getEncodedXmm(SrcVar->getRegNum());
+      (Asm->*(Emitter.XmmXmm))(Ty, VarReg, SrcReg);
+    } else {
+      x86::Address SrcStackAddr = static_cast<TargetX8632 *>(Func->getTarget())
+                                      ->stackVarToAsmOperand(SrcVar);
+      (Asm->*(Emitter.XmmAddr))(Ty, VarReg, SrcStackAddr);
+    }
+  } else if (const OperandX8632Mem *Mem =
+                 llvm::dyn_cast<OperandX8632Mem>(Src)) {
+    x86::Address SrcAddr = Mem->toAsmAddress(Asm);
+    (Asm->*(Emitter.XmmAddr))(Ty, VarReg, SrcAddr);
+  } else if (const ConstantInteger32 *Imm =
+                 llvm::dyn_cast<ConstantInteger32>(Src)) {
+    (Asm->*(Emitter.XmmImm))(Ty, VarReg, x86::Immediate(Imm->getValue()));
+  } else {
+    llvm_unreachable("Unexpected operand type");
+  }
+  Ostream &Str = Func->getContext()->getStrEmit();
+  emitIASBytes(Str, Asm, StartPosition);
+}
+
 void
 emitIASVarOperandTyXMM(const Cfg *Func, Type Ty, const Variable *Var,
                        const Operand *Src,
                        const x86::AssemblerX86::XmmEmitterTwoOps &Emitter) {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   assert(Var->hasReg());
   RegX8632::XmmRegister VarReg = RegX8632::getEncodedXmm(Var->getRegNum());
   if (const Variable *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     if (SrcVar->hasReg()) {
@@ skipping 135 matching lines @@
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Sbb::Emitter = {
     &x86::AssemblerX86::sbb, &x86::AssemblerX86::sbb, &x86::AssemblerX86::sbb};
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Sub::Emitter = {
     &x86::AssemblerX86::sub, &x86::AssemblerX86::sub, &x86::AssemblerX86::sub};
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Xor::Emitter = {
     &x86::AssemblerX86::Xor, &x86::AssemblerX86::Xor, &x86::AssemblerX86::Xor};
 
+// Binary Shift GPR ops
+template <>
+const x86::AssemblerX86::GPREmitterShiftOp InstX8632Rol::Emitter = {
+    &x86::AssemblerX86::rol, &x86::AssemblerX86::rol};
+template <>
+const x86::AssemblerX86::GPREmitterShiftOp InstX8632Sar::Emitter = {
+    &x86::AssemblerX86::sar, &x86::AssemblerX86::sar};
+template <>
+const x86::AssemblerX86::GPREmitterShiftOp InstX8632Shl::Emitter = {
+    &x86::AssemblerX86::shl, &x86::AssemblerX86::shl};
+template <>
+const x86::AssemblerX86::GPREmitterShiftOp InstX8632Shr::Emitter = {
+    &x86::AssemblerX86::shr, &x86::AssemblerX86::shr};
+
 // Binary XMM ops
 template <>
 const x86::AssemblerX86::XmmEmitterTwoOps InstX8632Addss::Emitter = {
     &x86::AssemblerX86::addss, &x86::AssemblerX86::addss, NULL};
 template <>
 const x86::AssemblerX86::XmmEmitterTwoOps InstX8632Addps::Emitter = {
     &x86::AssemblerX86::addps, &x86::AssemblerX86::addps, NULL};
 template <>
 const x86::AssemblerX86::XmmEmitterTwoOps InstX8632Divss::Emitter = {
     &x86::AssemblerX86::divss, &x86::AssemblerX86::divss, NULL};
@@ skipping 15 matching lines @@
 template <>
 const x86::AssemblerX86::XmmEmitterTwoOps InstX8632Pandn::Emitter = {
     &x86::AssemblerX86::pandn, &x86::AssemblerX86::pandn, NULL};
 template <>
 const x86::AssemblerX86::XmmEmitterTwoOps InstX8632Pcmpeq::Emitter = {
     &x86::AssemblerX86::pcmpeq, &x86::AssemblerX86::pcmpeq, NULL};
 template <>
 const x86::AssemblerX86::XmmEmitterTwoOps InstX8632Pcmpgt::Emitter = {
     &x86::AssemblerX86::pcmpgt, &x86::AssemblerX86::pcmpgt, NULL};
 template <>
+const x86::AssemblerX86::XmmEmitterTwoOps InstX8632Pmull::Emitter = {
+    &x86::AssemblerX86::pmull, &x86::AssemblerX86::pmull, NULL};
+template <>
 const x86::AssemblerX86::XmmEmitterTwoOps InstX8632Pmuludq::Emitter = {
     &x86::AssemblerX86::pmuludq, &x86::AssemblerX86::pmuludq, NULL};
 template <>
 const x86::AssemblerX86::XmmEmitterTwoOps InstX8632Por::Emitter = {
     &x86::AssemblerX86::por, &x86::AssemblerX86::por, NULL};
 template <>
 const x86::AssemblerX86::XmmEmitterTwoOps InstX8632Psub::Emitter = {
     &x86::AssemblerX86::psub, &x86::AssemblerX86::psub, NULL};
 template <>
 const x86::AssemblerX86::XmmEmitterTwoOps InstX8632Pxor::Emitter = {
     &x86::AssemblerX86::pxor, &x86::AssemblerX86::pxor, NULL};
 template <>
 const x86::AssemblerX86::XmmEmitterTwoOps InstX8632Subss::Emitter = {
     &x86::AssemblerX86::subss, &x86::AssemblerX86::subss, NULL};
 template <>
 const x86::AssemblerX86::XmmEmitterTwoOps InstX8632Subps::Emitter = {
     &x86::AssemblerX86::subps, &x86::AssemblerX86::subps, NULL};
 
+// Binary XMM Shift ops
+template <>
+const x86::AssemblerX86::XmmEmitterShiftOp InstX8632Psll::Emitter = {
+    &x86::AssemblerX86::psll, &x86::AssemblerX86::psll,
+    &x86::AssemblerX86::psll};
+template <>
+const x86::AssemblerX86::XmmEmitterShiftOp InstX8632Psra::Emitter = {
+    &x86::AssemblerX86::psra, &x86::AssemblerX86::psra,
+    &x86::AssemblerX86::psra};
+
 template <> void InstX8632Sqrtss::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Type Ty = getSrc(0)->getType();
   assert(isScalarFloatingType(Ty));
   Str << "\tsqrt" << TypeX8632Attributes[Ty].SdSsString << "\t";
   getDest()->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
   Str << "\n";
@@ skipping 23 matching lines @@
           TargetX8632::SSE4_1;
   (void)TypesAreValid;
   (void)InstructionSetIsValid;
   assert(TypesAreValid);
   assert(InstructionSetIsValid);
   snprintf(buf, llvm::array_lengthof(buf), "pmull%s",
            TypeX8632Attributes[getDest()->getType()].PackString);
   emitTwoAddress(buf, this, Func);
 }
 
+template <> void InstX8632Pmull::emitIAS(const Cfg *Func) const {
+  Type Ty = getDest()->getType();
+  bool TypesAreValid = Ty == IceType_v4i32 || Ty == IceType_v8i16;
+  bool InstructionSetIsValid =
+      Ty == IceType_v8i16 ||
+      static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() >=
+          TargetX8632::SSE4_1;
+  (void)TypesAreValid;
+  (void)InstructionSetIsValid;
+  assert(TypesAreValid);
+  assert(InstructionSetIsValid);
+  assert(getSrcSize() == 2);
+  Type ElementTy = typeElementType(Ty);
+  emitIASVarOperandTyXMM(Func, ElementTy, getDest(), getSrc(1), Emitter);
+}
+
 template <> void InstX8632Subss::emit(const Cfg *Func) const {
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "sub%s",
            TypeX8632Attributes[getDest()->getType()].SdSsString);
   emitTwoAddress(buf, this, Func);
 }
 
 template <> void InstX8632Psub::emit(const Cfg *Func) const {
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "psub%s",
@@ skipping 1282 matching lines @@
   }
   Str << "(";
   if (Func)
     Var->dump(Func);
   else
     Var->dump(Str);
   Str << ")";
 }
 
 } // end of namespace Ice