Rename Int32{UMod,UDiv} to Uint32{Div,Mod} and Int64{UMod,UDiv} to Uint64{Div,Mod}.

test/unittests/compiler/arm/instruction-selector-arm-unittest.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "test/unittests/compiler/instruction-selector-unittest.h"
 
 namespace v8 {
 namespace internal {
 namespace compiler {
 
@@ skipping 1562 matching lines @@
   m.Return(
       m.Int32Sub(m.Parameter(0), m.Int32Mul(m.Parameter(1), m.Parameter(2))));
   Stream s = m.Build(MLS);
   ASSERT_EQ(1U, s.size());
   EXPECT_EQ(kArmMls, s[0]->arch_opcode());
   EXPECT_EQ(1U, s[0]->OutputCount());
   EXPECT_EQ(3U, s[0]->InputCount());
 }
 
 
-TEST_F(InstructionSelectorTest, Int32UDivWithParameters) {
+TEST_F(InstructionSelectorTest, Uint32DivWithParameters) {
   StreamBuilder m(this, kMachInt32, kMachInt32, kMachInt32);
-  m.Return(m.Int32UDiv(m.Parameter(0), m.Parameter(1)));
+  m.Return(m.Uint32Div(m.Parameter(0), m.Parameter(1)));
   Stream s = m.Build();
   ASSERT_EQ(4U, s.size());
   EXPECT_EQ(kArmVcvtF64U32, s[0]->arch_opcode());
   ASSERT_EQ(1U, s[0]->OutputCount());
   EXPECT_EQ(kArmVcvtF64U32, s[1]->arch_opcode());
   ASSERT_EQ(1U, s[1]->OutputCount());
   EXPECT_EQ(kArmVdivF64, s[2]->arch_opcode());
   ASSERT_EQ(2U, s[2]->InputCount());
   ASSERT_EQ(1U, s[2]->OutputCount());
   EXPECT_EQ(s.ToVreg(s[0]->Output()), s.ToVreg(s[2]->InputAt(0)));
   EXPECT_EQ(s.ToVreg(s[1]->Output()), s.ToVreg(s[2]->InputAt(1)));
   EXPECT_EQ(kArmVcvtU32F64, s[3]->arch_opcode());
   ASSERT_EQ(1U, s[3]->InputCount());
   EXPECT_EQ(s.ToVreg(s[2]->Output()), s.ToVreg(s[3]->InputAt(0)));
 }
 
 
-TEST_F(InstructionSelectorTest, Int32UDivWithParametersForSUDIV) {
+TEST_F(InstructionSelectorTest, Uint32DivWithParametersForSUDIV) {
   StreamBuilder m(this, kMachInt32, kMachInt32, kMachInt32);
-  m.Return(m.Int32UDiv(m.Parameter(0), m.Parameter(1)));
+  m.Return(m.Uint32Div(m.Parameter(0), m.Parameter(1)));
   Stream s = m.Build(SUDIV);
   ASSERT_EQ(1U, s.size());
   EXPECT_EQ(kArmUdiv, s[0]->arch_opcode());
 }
 
 
-TEST_F(InstructionSelectorTest, Int32UModWithParameters) {
+TEST_F(InstructionSelectorTest, Uint32ModWithParameters) {
   StreamBuilder m(this, kMachInt32, kMachInt32, kMachInt32);
-  m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
+  m.Return(m.Uint32Mod(m.Parameter(0), m.Parameter(1)));
   Stream s = m.Build();
   ASSERT_EQ(6U, s.size());
   EXPECT_EQ(kArmVcvtF64U32, s[0]->arch_opcode());
   ASSERT_EQ(1U, s[0]->OutputCount());
   EXPECT_EQ(kArmVcvtF64U32, s[1]->arch_opcode());
   ASSERT_EQ(1U, s[1]->OutputCount());
   EXPECT_EQ(kArmVdivF64, s[2]->arch_opcode());
   ASSERT_EQ(2U, s[2]->InputCount());
   ASSERT_EQ(1U, s[2]->OutputCount());
   EXPECT_EQ(s.ToVreg(s[0]->Output()), s.ToVreg(s[2]->InputAt(0)));
   EXPECT_EQ(s.ToVreg(s[1]->Output()), s.ToVreg(s[2]->InputAt(1)));
   EXPECT_EQ(kArmVcvtU32F64, s[3]->arch_opcode());
   ASSERT_EQ(1U, s[3]->InputCount());
   EXPECT_EQ(s.ToVreg(s[2]->Output()), s.ToVreg(s[3]->InputAt(0)));
   EXPECT_EQ(kArmMul, s[4]->arch_opcode());
   ASSERT_EQ(1U, s[4]->OutputCount());
   ASSERT_EQ(2U, s[4]->InputCount());
   EXPECT_EQ(s.ToVreg(s[3]->Output()), s.ToVreg(s[4]->InputAt(0)));
   EXPECT_EQ(s.ToVreg(s[1]->InputAt(0)), s.ToVreg(s[4]->InputAt(1)));
   EXPECT_EQ(kArmSub, s[5]->arch_opcode());
   ASSERT_EQ(1U, s[5]->OutputCount());
   ASSERT_EQ(2U, s[5]->InputCount());
   EXPECT_EQ(s.ToVreg(s[0]->InputAt(0)), s.ToVreg(s[5]->InputAt(0)));
   EXPECT_EQ(s.ToVreg(s[4]->Output()), s.ToVreg(s[5]->InputAt(1)));
 }
 
 
-TEST_F(InstructionSelectorTest, Int32UModWithParametersForSUDIV) {
+TEST_F(InstructionSelectorTest, Uint32ModWithParametersForSUDIV) {
   StreamBuilder m(this, kMachInt32, kMachInt32, kMachInt32);
-  m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
+  m.Return(m.Uint32Mod(m.Parameter(0), m.Parameter(1)));
   Stream s = m.Build(SUDIV);
   ASSERT_EQ(3U, s.size());
   EXPECT_EQ(kArmUdiv, s[0]->arch_opcode());
   ASSERT_EQ(1U, s[0]->OutputCount());
   ASSERT_EQ(2U, s[0]->InputCount());
   EXPECT_EQ(kArmMul, s[1]->arch_opcode());
   ASSERT_EQ(1U, s[1]->OutputCount());
   ASSERT_EQ(2U, s[1]->InputCount());
   EXPECT_EQ(s.ToVreg(s[0]->Output()), s.ToVreg(s[1]->InputAt(0)));
   EXPECT_EQ(s.ToVreg(s[0]->InputAt(1)), s.ToVreg(s[1]->InputAt(1)));
   EXPECT_EQ(kArmSub, s[2]->arch_opcode());
   ASSERT_EQ(1U, s[2]->OutputCount());
   ASSERT_EQ(2U, s[2]->InputCount());
   EXPECT_EQ(s.ToVreg(s[0]->InputAt(0)), s.ToVreg(s[2]->InputAt(0)));
   EXPECT_EQ(s.ToVreg(s[1]->Output()), s.ToVreg(s[2]->InputAt(1)));
 }
 
 
-TEST_F(InstructionSelectorTest, Int32UModWithParametersForSUDIVAndMLS) {
+TEST_F(InstructionSelectorTest, Uint32ModWithParametersForSUDIVAndMLS) {
   StreamBuilder m(this, kMachInt32, kMachInt32, kMachInt32);
-  m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
+  m.Return(m.Uint32Mod(m.Parameter(0), m.Parameter(1)));
   Stream s = m.Build(MLS, SUDIV);
   ASSERT_EQ(2U, s.size());
   EXPECT_EQ(kArmUdiv, s[0]->arch_opcode());
   ASSERT_EQ(1U, s[0]->OutputCount());
   ASSERT_EQ(2U, s[0]->InputCount());
   EXPECT_EQ(kArmMls, s[1]->arch_opcode());
   ASSERT_EQ(1U, s[1]->OutputCount());
   ASSERT_EQ(3U, s[1]->InputCount());
   EXPECT_EQ(s.ToVreg(s[0]->Output()), s.ToVreg(s[1]->InputAt(0)));
   EXPECT_EQ(s.ToVreg(s[0]->InputAt(1)), s.ToVreg(s[1]->InputAt(1)));
@@ skipping 240 matching lines @@
       ASSERT_EQ(3U, s[0]->InputCount());
       EXPECT_EQ(lsb, s.ToInt32(s[0]->InputAt(1)));
       EXPECT_EQ(width, s.ToInt32(s[0]->InputAt(2)));
     }
   }
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8