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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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975 EMIT(0xD1); | 975 EMIT(0xD1); |
976 EMIT(0xD8 | dst.code()); | 976 EMIT(0xD8 | dst.code()); |
977 } else { | 977 } else { |
978 EMIT(0xC1); | 978 EMIT(0xC1); |
979 EMIT(0xD8 | dst.code()); | 979 EMIT(0xD8 | dst.code()); |
980 EMIT(imm8); | 980 EMIT(imm8); |
981 } | 981 } |
982 } | 982 } |
983 | 983 |
984 | 984 |
985 void Assembler::ror(Register dst, uint8_t imm8) { | 985 void Assembler::ror(const Operand& dst, uint8_t imm8) { |
986 EnsureSpace ensure_space(this); | 986 EnsureSpace ensure_space(this); |
987 DCHECK(is_uint5(imm8)); // illegal shift count | 987 DCHECK(is_uint5(imm8)); // illegal shift count |
988 if (imm8 == 1) { | 988 if (imm8 == 1) { |
989 EMIT(0xD1); | 989 EMIT(0xD1); |
990 EMIT(0xC8 | dst.code()); | 990 emit_operand(ecx, dst); |
991 } else { | 991 } else { |
992 EMIT(0xC1); | 992 EMIT(0xC1); |
993 EMIT(0xC8 | dst.code()); | 993 emit_operand(ecx, dst); |
994 EMIT(imm8); | 994 EMIT(imm8); |
995 } | 995 } |
996 } | 996 } |
997 | 997 |
998 | 998 |
999 void Assembler::ror_cl(Register dst) { | 999 void Assembler::ror_cl(const Operand& dst) { |
1000 EnsureSpace ensure_space(this); | 1000 EnsureSpace ensure_space(this); |
1001 EMIT(0xD3); | 1001 EMIT(0xD3); |
1002 EMIT(0xC8 | dst.code()); | 1002 emit_operand(ecx, dst); |
1003 } | 1003 } |
1004 | 1004 |
1005 | 1005 |
1006 void Assembler::sar(const Operand& dst, uint8_t imm8) { | 1006 void Assembler::sar(const Operand& dst, uint8_t imm8) { |
1007 EnsureSpace ensure_space(this); | 1007 EnsureSpace ensure_space(this); |
1008 DCHECK(is_uint5(imm8)); // illegal shift count | 1008 DCHECK(is_uint5(imm8)); // illegal shift count |
1009 if (imm8 == 1) { | 1009 if (imm8 == 1) { |
1010 EMIT(0xD1); | 1010 EMIT(0xD1); |
1011 emit_operand(edi, dst); | 1011 emit_operand(edi, dst); |
1012 } else { | 1012 } else { |
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2667 fprintf(coverage_log, "%s\n", file_line); | 2667 fprintf(coverage_log, "%s\n", file_line); |
2668 fflush(coverage_log); | 2668 fflush(coverage_log); |
2669 } | 2669 } |
2670 } | 2670 } |
2671 | 2671 |
2672 #endif | 2672 #endif |
2673 | 2673 |
2674 } } // namespace v8::internal | 2674 } } // namespace v8::internal |
2675 | 2675 |
2676 #endif // V8_TARGET_ARCH_IA32 | 2676 #endif // V8_TARGET_ARCH_IA32 |
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