Update our yasm copy to yasm 1.1.0 (Part 1: yasm side)...

third_party/yasm/patched-yasm/modules/arch/x86/x86id.c

 /*
  * x86 identifier recognition and instruction handling
  *
  *  Copyright (C) 2002-2007  Peter Johnson
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND OTHER CONTRIBUTORS ``AS IS''
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR OTHER CONTRIBUTORS BE
  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <ctype.h>
 #include <util.h>
-RCSID("$Id: x86id.c 2130 2008-10-07 05:38:11Z peter $");
+RCSID("$Id: x86id.c 2279 2010-01-19 07:57:43Z peter $");
 
 #include <libyasm.h>
 #include <libyasm/phash.h>
 
 #include "modules/arch/x86/x86arch.h"
 
 
 static const char *cpu_find_reverse(unsigned int cpu0, unsigned int cpu1,
                                     unsigned int cpu2);
 
 /* Opcode modifiers. */
 #define MOD_Gap     0   /* Eats a parameter / does nothing */
 #define MOD_PreAdd  1   /* Parameter adds to "special" prefix */
 #define MOD_Op0Add  2   /* Parameter adds to opcode byte 0 */
 #define MOD_Op1Add  3   /* Parameter adds to opcode byte 1 */
 #define MOD_Op2Add  4   /* Parameter adds to opcode byte 2 */
 #define MOD_SpAdd   5   /* Parameter adds to "spare" value */
 #define MOD_OpSizeR 6   /* Parameter replaces opersize */
 #define MOD_Imm8    7   /* Parameter is included as immediate byte */
 #define MOD_AdSizeR 8   /* Parameter replaces addrsize (jmp only) */
 #define MOD_DOpS64R 9   /* Parameter replaces default 64-bit opersize */
 #define MOD_Op1AddSp 10 /* Parameter is added as "spare" to opcode byte 2 */
 #define MOD_SetVEX  11  /* Parameter replaces internal VEX prefix value */
 
 /* GAS suffix flags for instructions */
 enum x86_gas_suffix_flags {
-    NONE = 0,
-    SUF_B = 1<<0,
-    SUF_W = 1<<1,
-    SUF_L = 1<<2,
-    SUF_Q = 1<<3,
-    SUF_S = 1<<4,
-    SUF_MASK = SUF_B|SUF_W|SUF_L|SUF_Q|SUF_S,
+    SUF_Z = 1<<0,   /* no suffix */
+    SUF_B = 1<<1,
+    SUF_W = 1<<2,
+    SUF_L = 1<<3,
+    SUF_Q = 1<<4,
+    SUF_S = 1<<5,
+    SUF_MASK = SUF_Z|SUF_B|SUF_W|SUF_L|SUF_Q|SUF_S,
 
     /* Flags only used in x86_insn_info */
-    GAS_ONLY = 1<<5,        /* Only available in GAS mode */
-    GAS_ILLEGAL = 1<<6,     /* Illegal in GAS mode */
-    GAS_NO_REV = 1<<7,      /* Don't reverse operands in GAS mode */
-
-    /* Flags only used in insnprefix_parse_data */
-    WEAK = 1<<5             /* Relaxed operand mode for GAS */
+    GAS_ONLY = 1<<6,        /* Only available in GAS mode */
+    GAS_ILLEGAL = 1<<7,     /* Illegal in GAS mode */
+    GAS_NO_REV = 1<<8       /* Don't reverse operands in GAS mode */
 };
 
 /* Miscellaneous flag tests for instructions */
 enum x86_misc_flags {
     /* These are tested against BITS==64. */
     ONLY_64 = 1<<0,         /* Only available in 64-bit mode */
     NOT_64 = 1<<1,          /* Not available (invalid) in 64-bit mode */
     /* These are tested against whether the base instruction is an AVX one. */
     ONLY_AVX = 1<<2,        /* Only available in AVX instruction */
     NOT_AVX = 1<<3          /* Not available (invalid) in AVX instruction */
@@ skipping 26 matching lines @@
      */
     OPT_MemOffs = 21,
     OPT_Imm1 = 22,      /* immediate, value=1 (for special-case shift) */
     /* immediate, does not contain SEG:OFF (for jmp/call) */
     OPT_ImmNotSegOff = 23,
     OPT_XMM0 = 24,      /* XMM0 */
     /* AX/EAX/RAX memory operand only (EA) [special case for SVM opcodes]
      */
     OPT_MemrAX = 25,
     /* EAX memory operand only (EA) [special case for SVM skinit opcode] */
-    OPT_MemEAX = 26,
-    /* SIMDReg with value equal to operand 0 SIMDReg */
-    OPT_SIMDRegMatch0 = 27
+    OPT_MemEAX = 26
 };
 
 enum x86_operand_size {
     /* any size acceptable/no size spec acceptable (dep. on strict) */
     OPS_Any = 0,
     /* 8/16/32/64/80/128/256 bits (from user or reg size) */
     OPS_8 = 1,
     OPS_16 = 2,
     OPS_32 = 3,
     OPS_64 = 4,
@@ skipping 27 matching lines @@
      */
     OPA_SpareEA = 7,
     /* relative jump (outputs a jmp instead of normal insn) */
     OPA_JmpRel = 8,
     /* operand size goes into address size (jmp only) */
     OPA_AdSizeR = 9,
     /* far jump (outputs a farjmp instead of normal insn) */
     OPA_JmpFar = 10,
     /* ea operand only sets address size (no actual ea field) */
     OPA_AdSizeEA = 11,
-    OPA_DREX = 12,  /* operand data goes into DREX "dest" field */
-    OPA_VEX = 13,   /* operand data goes into VEX "vvvv" field */
-    /* operand data goes into BOTH VEX "vvvv" field and ea field */
-    OPA_EAVEX = 14,
-    /* operand data goes into BOTH VEX "vvvv" field and spare field */
-    OPA_SpareVEX = 15,
+    OPA_VEX = 12,   /* operand data goes into VEX/XOP "vvvv" field */
+    /* operand data goes into BOTH VEX/XOP "vvvv" field and ea field */
+    OPA_EAVEX = 13,
+    /* operand data goes into BOTH VEX/XOP "vvvv" field and spare field */
+    OPA_SpareVEX = 14,
     /* operand data goes into upper 4 bits of immediate byte (VEX is4 field) */
-    OPA_VEXImmSrc = 16,
+    OPA_VEXImmSrc = 15,
     /* operand data goes into bottom 4 bits of immediate byte
      * (currently only VEX imz2 field)
      */
-    OPA_VEXImm = 17
+    OPA_VEXImm = 16
 };
 
 enum x86_operand_post_action {
     OPAP_None = 0,
     /* sign-extended imm8 that could expand to a large imm16/32 */
     OPAP_SImm8 = 1,
     /* could become a short opcode mov with bits=64 and a32 prefix */
     OPAP_ShortMov = 2,
     /* forced 16-bit address size (override ignored, no prefix) */
     OPAP_A16 = 3,
@@ skipping 40 matching lines @@
      * parse-time due to possibly dependent expressions.  For these, some
      * additional data (stored in the second byte of the opcode with a
      * one-byte opcode) is passed to later stages of the assembler with
      * flags set to indicate postponed actions.
      */
     unsigned int post_action:3;
 } x86_info_operand;
 
 typedef struct x86_insn_info {
     /* GAS suffix flags */
-    unsigned int gas_flags:8;      /* Enabled for these GAS suffixes */
+    unsigned int gas_flags:9;      /* Enabled for these GAS suffixes */
 
-    /* Tests against BITS==64 and AVX */
-    unsigned int misc_flags:6;
+    /* Tests against BITS==64, AVX, and XOP */
+    unsigned int misc_flags:5;
 
     /* The CPU feature flags needed to execute this instruction.  This is OR'ed
      * with arch-specific data[2].  This combined value is compared with
      * cpu_enabled to see if all bits set here are set in cpu_enabled--if so,
      * the instruction is available on this CPU.
      */
     unsigned int cpu0:6;
     unsigned int cpu1:6;
     unsigned int cpu2:6;
 
@@ skipping 17 matching lines @@
      * to be *after* the F2/F3/66 "prefix").
      * (0=no special prefix)
      * 0xC0 - 0xCF indicate a VEX prefix, with the four LSBs holding "WLpp":
      *  W: VEX.W field (meaning depends on opcode)
      *  L: 0=128-bit, 1=256-bit
      *  pp: SIMD prefix designation:
      *      00: None
      *      01: 66
      *      10: F3
      *      11: F2
+     * 0x80 - 0x8F indicate a XOP prefix, with the four LSBs holding "WLpp":
+     *  same meanings as VEX prefix.
      */
     unsigned char special_prefix;
 
-    /* The DREX base byte value (almost).  The only bit kept from this
-     * value is the OC0 bit (0x08).  The MSB (0x80) of this value indicates
-     * if the DREX byte needs to be present in the instruction.
-     */
-#define NEED_DREX_MASK 0x80
-#define DREX_OC0_MASK 0x08
-    unsigned char drex_oc0;
-
     /* The length of the basic opcode */
     unsigned char opcode_len;
 
     /* The basic 1-3 byte opcode (not including the special instruction
      * prefix).
      */
     unsigned char opcode[3];
 
     /* The 3-bit "spare" value (extended opcode) for the R/M byte field */
     unsigned char spare;
@@ skipping 19 matching lines @@
     /* Modifier data */
     unsigned char mod_data[3];
 
     /* Number of elements in the instruction parse group */
     unsigned int num_info:8;
 
     /* BITS setting active at the time of parsing the instruction */
     unsigned int mode_bits:8;
 
     /* Suffix flags */
-    unsigned int suffix:8;
+    unsigned int suffix:9;
 
     /* Tests against BITS==64 and AVX */
-    unsigned int misc_flags:6;
+    unsigned int misc_flags:5;
 
     /* Parser enabled at the time of parsing the instruction */
     unsigned int parser:2;
 
     /* Strict forced setting at the time of parsing the instruction */
     unsigned int force_strict:1;
 
     /* Default rel setting at the time of parsing the instruction */
     unsigned int default_rel:1;
 } x86_id_insn;
@@ skipping 43 matching lines @@
         op->type = YASM_INSN__OPERAND_REG;
         op = yasm_insn_op_next(op);
     }
 }
 
 static void
 x86_finalize_jmpfar(yasm_bytecode *bc, yasm_bytecode *prev_bc,
                     const x86_insn_info *info)
 {
     x86_id_insn *id_insn = (x86_id_insn *)bc->contents;
+    unsigned char *mod_data = id_insn->mod_data;
     unsigned int mode_bits = id_insn->mode_bits;
     x86_jmpfar *jmpfar;
     yasm_insn_operand *op;
+    unsigned int i;
 
     jmpfar = yasm_xmalloc(sizeof(x86_jmpfar));
     x86_finalize_common(&jmpfar->common, info, mode_bits);
     x86_finalize_opcode(&jmpfar->opcode, info);
 
     op = yasm_insn_ops_first(&id_insn->insn);
 
     if (op->type == YASM_INSN__OPERAND_IMM && op->seg) {
         /* SEG:OFF */
         if (yasm_value_finalize_expr(&jmpfar->segment, op->seg, prev_bc, 16))
             yasm_error_set(YASM_ERROR_TOO_COMPLEX,
                            N_("jump target segment too complex"));
         if (yasm_value_finalize_expr(&jmpfar->offset, op->data.val, prev_bc,
                                      0))
             yasm_error_set(YASM_ERROR_TOO_COMPLEX,
                            N_("jump target offset too complex"));
     } else if (op->targetmod == X86_FAR) {
         /* "FAR imm" target needs to become "seg imm:imm". */
         yasm_expr *e = yasm_expr_create_branch(YASM_EXPR_SEG,
                                                yasm_expr_copy(op->data.val),
                                                op->data.val->line);
         if (yasm_value_finalize_expr(&jmpfar->offset, op->data.val, prev_bc, 0)
             || yasm_value_finalize_expr(&jmpfar->segment, e, prev_bc, 16))
             yasm_error_set(YASM_ERROR_TOO_COMPLEX,
                            N_("jump target expression too complex"));
+    } else if (yasm_insn_op_next(op)) {
+        /* Two operand form (gas) */
+        yasm_insn_operand *op2 = yasm_insn_op_next(op);
+        if (yasm_value_finalize_expr(&jmpfar->segment, op->data.val, prev_bc,
+                                     16))
+            yasm_error_set(YASM_ERROR_TOO_COMPLEX,
+                           N_("jump target segment too complex"));
+        if (yasm_value_finalize_expr(&jmpfar->offset, op2->data.val, prev_bc,
+                                     0))
+            yasm_error_set(YASM_ERROR_TOO_COMPLEX,
+                           N_("jump target offset too complex"));
+        if (op2->size == OPS_BITS)
+            jmpfar->common.opersize = (unsigned char)mode_bits;
     } else
         yasm_internal_error(N_("didn't get FAR expression in jmpfar"));
 
+    /* Apply modifiers */
+    for (i=0; i<NELEMS(info->modifiers); i++) {
+        switch (info->modifiers[i]) {
+            case MOD_Gap:
+                break;
+            case MOD_Op0Add:
+                jmpfar->opcode.opcode[0] += mod_data[i];
+                break;
+            case MOD_Op1Add:
+                jmpfar->opcode.opcode[1] += mod_data[i];
+                break;
+            case MOD_Op2Add:
+                jmpfar->opcode.opcode[2] += mod_data[i];
+                break;
+            case MOD_Op1AddSp:
+                jmpfar->opcode.opcode[1] += mod_data[i]<<3;
+                break;
+            default:
+                break;
+        }
+    }
+
     yasm_x86__bc_apply_prefixes((x86_common *)jmpfar, NULL,
                                 info->def_opersize_64,
                                 id_insn->insn.num_prefixes,
                                 id_insn->insn.prefixes);
 
     x86_id_insn_clear_operands(id_insn);
 
     /* Transform the bytecode */
     yasm_x86__bc_transform_jmpfar(bc, jmpfar);
 }
@@ skipping 169 matching lines @@
         if ((id_insn->misc_flags & ONLY_AVX) && (misc_flags & NOT_AVX))
             continue;
 
         /* Match parser mode */
         if ((gas_flags & GAS_ONLY) && id_insn->parser != X86_PARSER_GAS)
             continue;
         if ((gas_flags & GAS_ILLEGAL) && id_insn->parser == X86_PARSER_GAS)
             continue;
 
         /* Match suffix (if required) */
-        if (suffix != 0 && suffix != WEAK
+        if (id_insn->parser == X86_PARSER_GAS
             && ((suffix & SUF_MASK) & (gas_flags & SUF_MASK)) == 0)
             continue;
 
         /* Use reversed operands in GAS mode if not otherwise specified */
         use_ops = ops;
         if (id_insn->parser == X86_PARSER_GAS && !(gas_flags & GAS_NO_REV))
             use_ops = rev_ops;
 
         if (id_insn->insn.num_operands == 0) {
             found = 1;      /* no operands -> must have a match here. */
@@ skipping 32 matching lines @@
                     }
                     break;
                 case OPT_Mem:
                     if (op->type != YASM_INSN__OPERAND_MEMORY)
                         mismatch = 1;
                     break;
                 case OPT_SIMDRM:
                     if (op->type == YASM_INSN__OPERAND_MEMORY)
                         break;
                     /*@fallthrough@*/
-                case OPT_SIMDRegMatch0:
                 case OPT_SIMDReg:
                     if (op->type != YASM_INSN__OPERAND_REG)
                         mismatch = 1;
                     else {
                         switch ((x86_expritem_reg_size)(op->data.reg&~0xFUL)) {
                             case X86_MMXREG:
                             case X86_XMMREG:
                             case X86_YMMREG:
                                 break;
                             default:
                                 mismatch = 1;
                                 break;
                         }
                     }
-                    if (!mismatch && info_ops[i].type == OPT_SIMDRegMatch0 &&
-                        bypass != 7 && op->data.reg != use_ops[0]->data.reg)
-                        mismatch = 1;
                     break;
                 case OPT_SegReg:
                     if (op->type != YASM_INSN__OPERAND_SEGREG)
                         mismatch = 1;
                     break;
                 case OPT_CRReg:
                     if (op->type != YASM_INSN__OPERAND_REG ||
                         (op->data.reg & ~0xFUL) != X86_CRREG)
                         mismatch = 1;
                     break;
@@ skipping 134 matching lines @@
                 }
                 default:
                     yasm_internal_error(N_("invalid operand type"));
             }
 
             if (mismatch)
                 break;
 
             /* Check operand size */
             size = size_lookup[info_ops[i].size];
-            if (suffix != 0) {
+            if (id_insn->parser == X86_PARSER_GAS) {
                 /* Require relaxed operands for GAS mode (don't allow
                  * per-operand sizing).
                  */
                 if (op->type == YASM_INSN__OPERAND_REG && op->size == 0) {
                     /* Register size must exactly match */
                     if (yasm_x86__get_reg_size(op->data.reg) != size)
                         mismatch = 1;
                 } else if ((info_ops[i].type == OPT_Imm
                             || info_ops[i].type == OPT_ImmNotSegOff
                             || info_ops[i].type == OPT_Imm1)
@@ skipping 21 matching lines @@
                         if (op->size != size)
                             mismatch = 1;
                     }
                 }
             }
 
             if (mismatch)
                 break;
 
             /* Check for 64-bit effective address size in NASM mode */
-            if (suffix == 0 && op->type == YASM_INSN__OPERAND_MEMORY) {
+            if (id_insn->parser != X86_PARSER_GAS &&
+                op->type == YASM_INSN__OPERAND_MEMORY) {
                 if (info_ops[i].eas64) {
                     if (op->data.ea->disp.size != 64)
                         mismatch = 1;
                 } else if (op->data.ea->disp.size == 64)
                     mismatch = 1;
             }
 
             if (mismatch)
                 break;
 
@@ skipping 103 matching lines @@
     x86_id_insn *id_insn = (x86_id_insn *)bc->contents;
     x86_insn *insn;
     const x86_insn_info *info = id_insn->group;
     unsigned int mode_bits = id_insn->mode_bits;
     unsigned char *mod_data = id_insn->mod_data;
     yasm_insn_operand *op, *ops[5], *rev_ops[5];
     /*@null@*/ yasm_expr *imm;
     unsigned char im_len;
     unsigned char im_sign;
     unsigned char spare;
-    unsigned char drex;
-    unsigned char *pdrex;
     unsigned char vexdata, vexreg;
     unsigned int i;
     unsigned int size_lookup[] = {0, 8, 16, 32, 64, 80, 128, 256, 0};
     unsigned long do_postop = 0;
 
     size_lookup[OPS_BITS] = mode_bits;
 
     yasm_insn_finalize(&id_insn->insn);
 
     /* Build local array of operands from list, since we know we have a max
@@ skipping 72 matching lines @@
 
     /* Copy what we can from info */
     insn = yasm_xmalloc(sizeof(x86_insn));
     x86_finalize_common(&insn->common, info, mode_bits);
     x86_finalize_opcode(&insn->opcode, info);
     insn->x86_ea = NULL;
     imm = NULL;
     insn->def_opersize_64 = info->def_opersize_64;
     insn->special_prefix = info->special_prefix;
     spare = info->spare;
-    drex = info->drex_oc0 & DREX_OC0_MASK;
     vexdata = 0;
     vexreg = 0;
     im_len = 0;
     im_sign = 0;
     insn->postop = X86_POSTOP_NONE;
     insn->rex = 0;
-    pdrex = (info->drex_oc0 & NEED_DREX_MASK) ? &drex : NULL;
 
-    /* Move VEX data (stored in special prefix) to separate location to
+    /* Move VEX/XOP data (stored in special prefix) to separate location to
      * allow overriding of special prefix by modifiers.
      */
-    if ((insn->special_prefix & 0xF0) == 0xC0) {
+    if ((insn->special_prefix & 0xF0) == 0xC0 ||
+        (insn->special_prefix & 0xF0) == 0x80) {
         vexdata = insn->special_prefix;
         insn->special_prefix = 0;
     }
 
     /* Apply modifiers */
     for (i=0; i<NELEMS(info->modifiers); i++) {
         switch (info->modifiers[i]) {
             case MOD_Gap:
                 break;
             case MOD_PreAdd:
@@ skipping 67 matching lines @@
                             yasm_expr_destroy(op->data.val);
                             break;
                     }
                     break;
                 case OPA_EA:
                     switch (op->type) {
                         case YASM_INSN__OPERAND_REG:
                             insn->x86_ea =
                                 yasm_x86__ea_create_reg(insn->x86_ea,
                                     (unsigned long)op->data.reg, &insn->rex,
-                                    pdrex, mode_bits);
+                                    mode_bits);
                             break;
                         case YASM_INSN__OPERAND_SEGREG:
                             yasm_internal_error(
                                 N_("invalid operand conversion"));
                         case YASM_INSN__OPERAND_MEMORY:
                             if (op->seg)
                                 yasm_error_set(YASM_ERROR_VALUE,
                                     N_("invalid segment in effective address"));
                             insn->x86_ea = (x86_effaddr *)op->data.ea;
                             if (info_ops[i].type == OPT_MemOffs)
@@ skipping 16 matching lines @@
                                     op->data.val,
                                     size_lookup[info_ops[i].size]);
                             break;
                     }
                     break;
                 case OPA_EAVEX:
                     if (op->type != YASM_INSN__OPERAND_REG)
                         yasm_internal_error(N_("invalid operand conversion"));
                     insn->x86_ea =
                         yasm_x86__ea_create_reg(insn->x86_ea,
-                            (unsigned long)op->data.reg, &insn->rex, pdrex,
-                            mode_bits);
+                            (unsigned long)op->data.reg, &insn->rex, mode_bits);
                     vexreg = op->data.reg & 0xF;
                     break;
                 case OPA_Imm:
                     if (op->seg)
                         yasm_error_set(YASM_ERROR_VALUE,
                                        N_("immediate does not support segment"));
                     if (op->type == YASM_INSN__OPERAND_IMM) {
                         imm = op->data.val;
                         im_len = size_lookup[info_ops[i].size];
                     } else
                         yasm_internal_error(N_("invalid operand conversion"));
                     break;
                 case OPA_SImm:
                     if (op->seg)
                         yasm_error_set(YASM_ERROR_VALUE,
                                        N_("immediate does not support segment"));
                     if (op->type == YASM_INSN__OPERAND_IMM) {
                         imm = op->data.val;
                         im_len = size_lookup[info_ops[i].size];
                         im_sign = 1;
                     } else
                         yasm_internal_error(N_("invalid operand conversion"));
                     break;
                 case OPA_Spare:
                     if (op->type == YASM_INSN__OPERAND_SEGREG)
                         spare = (unsigned char)(op->data.reg&7);
                     else if (op->type == YASM_INSN__OPERAND_REG) {
-                        if (yasm_x86__set_rex_from_reg(&insn->rex, pdrex,
-                                &spare, op->data.reg, mode_bits, X86_REX_R))
+                        if (yasm_x86__set_rex_from_reg(&insn->rex, &spare,
+                                op->data.reg, mode_bits, X86_REX_R))
                             return;
                     } else
                         yasm_internal_error(N_("invalid operand conversion"));
                     break;
                 case OPA_SpareVEX:
                     if (op->type != YASM_INSN__OPERAND_REG)
                         yasm_internal_error(N_("invalid operand conversion"));
-                    if (yasm_x86__set_rex_from_reg(&insn->rex, pdrex,
-                            &spare, op->data.reg, mode_bits, X86_REX_R))
+                    if (yasm_x86__set_rex_from_reg(&insn->rex, &spare,
+                            op->data.reg, mode_bits, X86_REX_R))
                         return;
                     vexreg = op->data.reg & 0xF;
                     break;
                 case OPA_Op0Add:
                     if (op->type == YASM_INSN__OPERAND_REG) {
                         unsigned char opadd;
-                        if (yasm_x86__set_rex_from_reg(&insn->rex, pdrex,
-                                &opadd, op->data.reg, mode_bits, X86_REX_B))
+                        if (yasm_x86__set_rex_from_reg(&insn->rex, &opadd,
+                                op->data.reg, mode_bits, X86_REX_B))
                             return;
                         insn->opcode.opcode[0] += opadd;
                     } else
                         yasm_internal_error(N_("invalid operand conversion"));
                     break;
                 case OPA_Op1Add:
                     if (op->type == YASM_INSN__OPERAND_REG) {
                         unsigned char opadd;
-                        if (yasm_x86__set_rex_from_reg(&insn->rex, pdrex,
-                                &opadd, op->data.reg, mode_bits, X86_REX_B))
+                        if (yasm_x86__set_rex_from_reg(&insn->rex, &opadd,
+                                op->data.reg, mode_bits, X86_REX_B))
                             return;
                         insn->opcode.opcode[1] += opadd;
                     } else
                         yasm_internal_error(N_("invalid operand conversion"));
                     break;
                 case OPA_SpareEA:
                     if (op->type == YASM_INSN__OPERAND_REG) {
                         insn->x86_ea =
                             yasm_x86__ea_create_reg(insn->x86_ea,
                                 (unsigned long)op->data.reg, &insn->rex,
-                                pdrex, mode_bits);
+                                mode_bits);
                         if (!insn->x86_ea ||
-                            yasm_x86__set_rex_from_reg(&insn->rex, pdrex,
-                                &spare, op->data.reg, mode_bits, X86_REX_R)) {
+                            yasm_x86__set_rex_from_reg(&insn->rex, &spare,
+                                op->data.reg, mode_bits, X86_REX_R)) {
                             if (insn->x86_ea)
                                 yasm_xfree(insn->x86_ea);
                             yasm_xfree(insn);
                             return;
                         }
                     } else
                         yasm_internal_error(N_("invalid operand conversion"));
                     break;
                 case OPA_AdSizeEA: {
                     const uintptr_t *regp = NULL;
@@ skipping 12 matching lines @@
                     else if (*regp == (X86_REG32 | 0))
                         insn->common.addrsize = 32;
                     else if (mode_bits == 64 && *regp == (X86_REG64 | 0))
                         insn->common.addrsize = 64;
                     else
                         yasm_error_set(YASM_ERROR_TYPE,
                             N_("unsupported address size"));
                     yasm_x86__ea_destroy(op->data.ea);
                     break;
                 }
-                case OPA_DREX:
-                    if (op->type == YASM_INSN__OPERAND_REG) {
-                        drex &= 0x0F;
-                        drex |= (op->data.reg << 4) & 0xF0;
-                    } else
-                        yasm_internal_error(N_("invalid operand conversion"));
-                    break;
                 case OPA_VEX:
                     if (op->type != YASM_INSN__OPERAND_REG)
                         yasm_internal_error(N_("invalid operand conversion"));
                     vexreg = op->data.reg & 0xF;
                     break;
                 case OPA_VEXImmSrc:
                     if (op->type != YASM_INSN__OPERAND_REG)
                         yasm_internal_error(N_("invalid operand conversion"));
 
                     if (!imm) {
@@ skipping 74 matching lines @@
                     do_postop = OPAP_SImm32Avail;
                     break;
                 default:
                     yasm_internal_error(
                         N_("unknown operand postponed action"));
             }
         }
     }
 
     if (insn->x86_ea) {
-        yasm_x86__ea_init(insn->x86_ea, spare, drex,
-                          (unsigned int)(info->drex_oc0 & NEED_DREX_MASK),
-                          prev_bc);
+        yasm_x86__ea_init(insn->x86_ea, spare, prev_bc);
         for (i=0; i<id_insn->insn.num_segregs; i++)
             yasm_ea_set_segreg(&insn->x86_ea->ea, id_insn->insn.segregs[i]);
     } else if (id_insn->insn.num_segregs > 0 && insn->special_prefix == 0) {
         if (id_insn->insn.num_segregs > 1)
             yasm_warn_set(YASM_WARN_GENERAL,
                           N_("multiple segment overrides, using leftmost"));
         insn->special_prefix = (unsigned char)
             (id_insn->insn.segregs[id_insn->insn.num_segregs-1]>>8);
     } else if (id_insn->insn.num_segregs > 0)
         yasm_internal_error(N_("unhandled segment prefix"));
@@ skipping 49 matching lines @@
                 (yasm_expr_get_intnum(&insn->imm->abs, 0) &&
                  yasm_intnum_check_size(
                     yasm_expr_get_intnum(&insn->imm->abs, 0), 32, 0, 1))) {
                 /* Throwaway REX byte */
                 unsigned char rex_temp = 0;
 
                 /* Build ModRM EA - CAUTION: this depends on
                  * opcode 0 being a mov instruction!
                  */
                 insn->x86_ea = yasm_x86__ea_create_reg(insn->x86_ea,
-                    (unsigned long)insn->opcode.opcode[0]-0xB8, &rex_temp,
-                    NULL, 64);
+                    (unsigned long)insn->opcode.opcode[0]-0xB8, &rex_temp, 64);
 
                 /* Make the imm32s form permanent. */
                 insn->opcode.opcode[0] = insn->opcode.opcode[1];
                 insn->imm->size = 32;
             }
             insn->opcode.opcode[1] = 0; /* avoid possible confusion */
             break;
         default:
             break;
     }
 
-    /* Convert to VEX prefixes if requested.
-     * To save space in the insn structure, the VEX prefix is written into
+    /* Convert to VEX/XOP prefixes if requested.
+     * To save space in the insn structure, the VEX/XOP prefix is written into
      * special_prefix and the first 2 bytes of the instruction are set to
-     * the second two VEX bytes.  During calc_len() it may be shortened to
-     * one VEX byte (this can only be done after knowledge of REX value).
+     * the second two VEX/XOP bytes.  During calc_len() it may be shortened to
+     * one VEX byte (this can only be done after knowledge of REX value); this
+     * further optimization is not possible for XOP.
      */
     if (vexdata) {
+        int xop = ((vexdata & 0xF0) == 0x80);
         unsigned char vex1 = 0xE0;  /* R=X=B=1, mmmmm=0 */
         unsigned char vex2;
-        /* Look at the first bytes of the opcode to see what leading bytes
-         * to encode in the VEX mmmmm field.  Leave R=X=B=1 for now.
-         */
-        if (insn->opcode.opcode[0] != 0x0F)
-            yasm_internal_error(N_("first opcode byte of VEX must be 0x0F"));
 
-        if (insn->opcode.opcode[1] == 0x38)
-            vex1 |= 0x02;       /* implied 0x0F 0x38 */
-        else if (insn->opcode.opcode[1] == 0x3A)
-            vex1 |= 0x03;       /* implied 0x0F 0x3A */
-        else {
-            /* Originally a 0F-only opcode; move opcode byte back one position
-             * to make room for VEX prefix.
+        if (xop) {
+            /* Look at the first bytes of the opcode for the XOP mmmmm field.
+             * Leave R=X=B=1 for now.
              */
+            if (insn->opcode.opcode[0] != 0x08 &&
+                insn->opcode.opcode[0] != 0x09)
+                yasm_internal_error(N_("first opcode byte of XOP must be 0x08 or 0x09"));
+            vex1 |= insn->opcode.opcode[0];
+            /* Move opcode byte back one byte to make room for XOP prefix. */
             insn->opcode.opcode[2] = insn->opcode.opcode[1];
-            vex1 |= 0x01;       /* implied 0x0F */
+        } else {
+            /* Look at the first bytes of the opcode to see what leading bytes
+             * to encode in the VEX mmmmm field.  Leave R=X=B=1 for now.
+             */
+            if (insn->opcode.opcode[0] != 0x0F)
+                yasm_internal_error(N_("first opcode byte of VEX must be 0x0F"));
+
+            if (insn->opcode.opcode[1] == 0x38)
+                vex1 |= 0x02;       /* implied 0x0F 0x38 */
+            else if (insn->opcode.opcode[1] == 0x3A)
+                vex1 |= 0x03;       /* implied 0x0F 0x3A */
+            else {
+                /* Originally a 0F-only opcode; move opcode byte back one
+                 * position to make room for VEX prefix.
+                 */
+                insn->opcode.opcode[2] = insn->opcode.opcode[1];
+                vex1 |= 0x01;       /* implied 0x0F */
+            }
         }
 
         /* Check for update of special prefix by modifiers */
         if (insn->special_prefix != 0) {
             vexdata &= ~0x03;
             switch (insn->special_prefix) {
                 case 0x66:
                     vexdata |= 0x01;
                     break;
                 case 0xF3:
                     vexdata |= 0x02;
                     break;
                 case 0xF2:
                     vexdata |= 0x03;
                     break;
                 default:
                     yasm_internal_error(N_("unrecognized special prefix"));
             }
         }
 
         /* 2nd VEX byte is WvvvvLpp.
          * W, L, pp come from vexdata
          * vvvv comes from 1s complement of vexreg
          */
         vex2 = (((vexdata & 0x8) << 4) |                /* W */
                 ((15 - (vexreg & 0xF)) << 3) |          /* vvvv */
                 (vexdata & 0x7));                       /* Lpp */
 
         /* Save to special_prefix and opcode */
-        insn->special_prefix = 0xC4;    /* VEX prefix */
+        insn->special_prefix = xop ? 0x8F : 0xC4;   /* VEX/XOP prefix */
         insn->opcode.opcode[0] = vex1;
         insn->opcode.opcode[1] = vex2;
         insn->opcode.len = 3;   /* two prefix bytes and 1 opcode byte */
     }
 
     x86_id_insn_clear_operands(id_insn);
 
     /* Transform the bytecode */
     yasm_x86__bc_transform_insn(bc, insn);
 }
@@ skipping 129 matching lines @@
 
     *bc = (yasm_bytecode *)NULL;
     *prefix = 0;
 
     if (id_len > 16)
         return YASM_ARCH_NOTINSNPREFIX;
     for (i=0; i<id_len; i++)
         lcaseid[i] = tolower(id[i]);
     lcaseid[id_len] = '\0';
 
-    switch (arch_x86->parser) {
+    switch (PARSER(arch_x86)) {
         case X86_PARSER_NASM:
             pdata = insnprefix_nasm_find(lcaseid, id_len);
             break;
         case X86_PARSER_TASM:
             pdata = insnprefix_nasm_find(lcaseid, id_len);
             break;
         case X86_PARSER_GAS:
             pdata = insnprefix_gas_find(lcaseid, id_len);
             break;
         default:
@@ skipping 19 matching lines @@
             yasm_insn_initialize(&id_insn->insn);
             id_insn->group = not64_insn;
             id_insn->cpu_enabled = cpu_enabled;
             id_insn->mod_data[0] = 0;
             id_insn->mod_data[1] = 0;
             id_insn->mod_data[2] = 0;
             id_insn->num_info = NELEMS(not64_insn);
             id_insn->mode_bits = arch_x86->mode_bits;
             id_insn->suffix = 0;
             id_insn->misc_flags = 0;
-            id_insn->parser = arch_x86->parser;
+            id_insn->parser = PARSER(arch_x86);
+        
             id_insn->force_strict = arch_x86->force_strict != 0;
             id_insn->default_rel = arch_x86->default_rel != 0;
             *bc = yasm_bc_create_common(&x86_id_insn_callback, id_insn, line);
             return YASM_ARCH_INSN;
         }
 
         cpu0 = pdata->cpu0;
         cpu1 = pdata->cpu1;
         cpu2 = pdata->cpu2;
 
@@ skipping 10 matching lines @@
         yasm_insn_initialize(&id_insn->insn);
         id_insn->group = pdata->group;
         id_insn->cpu_enabled = cpu_enabled;
         id_insn->mod_data[0] = pdata->mod_data0;
         id_insn->mod_data[1] = pdata->mod_data1;
         id_insn->mod_data[2] = pdata->mod_data2;
         id_insn->num_info = pdata->num_info;
         id_insn->mode_bits = arch_x86->mode_bits;
         id_insn->suffix = pdata->flags;
         id_insn->misc_flags = pdata->misc_flags;
-        id_insn->parser = arch_x86->parser;
+        id_insn->parser = PARSER(arch_x86);
         id_insn->force_strict = arch_x86->force_strict != 0;
         id_insn->default_rel = arch_x86->default_rel != 0;
         *bc = yasm_bc_create_common(&x86_id_insn_callback, id_insn, line);
         return YASM_ARCH_INSN;
     } else {
         unsigned long type = pdata->num_info<<8;
         unsigned long value = pdata->flags;
 
         if (arch_x86->mode_bits == 64 && type == X86_OPERSIZE && value == 32) {
             yasm_error_set(YASM_ERROR_GENERAL,
@@ skipping 40 matching lines @@
     x86_id_insn *id_insn = yasm_xmalloc(sizeof(x86_id_insn));
 
     yasm_insn_initialize(&id_insn->insn);
     id_insn->group = empty_insn;
     id_insn->cpu_enabled = arch_x86->cpu_enables[arch_x86->active_cpu];
     id_insn->mod_data[0] = 0;
     id_insn->mod_data[1] = 0;
     id_insn->mod_data[2] = 0;
     id_insn->num_info = NELEMS(empty_insn);
     id_insn->mode_bits = arch_x86->mode_bits;
-    id_insn->suffix = 0;
+    id_insn->suffix = (PARSER(arch_x86) == X86_PARSER_GAS) ? SUF_Z : 0;
     id_insn->misc_flags = 0;
-    id_insn->parser = arch_x86->parser;
+    id_insn->parser = PARSER(arch_x86);
     id_insn->force_strict = arch_x86->force_strict != 0;
     id_insn->default_rel = arch_x86->default_rel != 0;
 
     return yasm_bc_create_common(&x86_id_insn_callback, id_insn, line);
 }