Update our yasm copy to yasm 1.1.0 (Part 1: yasm side)...

third_party/yasm/patched-yasm/modules/arch/x86/x86arch.h

-/* $Id: x86arch.h 2181 2009-03-20 07:36:49Z peter $
+/* $Id: x86arch.h 2346 2010-08-01 01:37:37Z peter $
  * x86 Architecture header file
  *
  *  Copyright (C) 2001-2007  Peter Johnson
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
@@ skipping 45 matching lines @@
 #define CPU_Undoc   23      /* Undocumented instruction */
 #define CPU_Obs     24      /* Obsolete instruction */
 #define CPU_Priv    25      /* Priveleged instruction */
 #define CPU_SVM     26      /* Secure Virtual Machine instruction */
 #define CPU_PadLock 27      /* VIA PadLock instruction */
 #define CPU_EM64T   28      /* Intel EM64T or better */
 #define CPU_SSSE3   29      /* Streaming SIMD extensions 3 required */
 #define CPU_SSE41   30      /* Streaming SIMD extensions 4.1 required */
 #define CPU_SSE42   31      /* Streaming SIMD extensions 4.2 required */
 #define CPU_SSE4a   32      /* AMD Streaming SIMD extensions 4a required */
-#define CPU_SSE5    33      /* AMD Streaming SIMD extensions 5 required */
-#define CPU_XSAVE   34      /* Intel XSAVE instructions */
-#define CPU_AVX     35      /* Intel Advanced Vector Extensions */
-#define CPU_FMA     36      /* Intel Fused-Multiply-Add Extensions */
-#define CPU_AES     37      /* AES instruction */
-#define CPU_CLMUL   38      /* PCLMULQDQ instruction */
-#define CPU_MOVBE   39      /* MOVBE instruction */
+#define CPU_XSAVE   33      /* Intel XSAVE instructions */
+#define CPU_AVX     34      /* Intel Advanced Vector Extensions */
+#define CPU_FMA     35      /* Intel Fused-Multiply-Add Extensions */
+#define CPU_AES     36      /* AES instruction */
+#define CPU_CLMUL   37      /* PCLMULQDQ instruction */
+#define CPU_MOVBE   38      /* MOVBE instruction */
+#define CPU_XOP     39      /* AMD XOP extensions */
+#define CPU_FMA4    40      /* AMD Fused-Multiply-Add extensions */
+#define CPU_F16C    41      /* Intel float-16 instructions */
+#define CPU_FSGSBASE 42     /* Intel FSGSBASE instructions */
+#define CPU_RDRAND  43      /* Intel RDRAND instruction */
+#define CPU_XSAVEOPT 44     /* Intel XSAVEOPT instruction */
+#define CPU_EPTVPID 45      /* Intel INVEPT, INVVPID instructions */
+#define CPU_SMX     46      /* Intel SMX instruction (GETSEC) */
+
+enum x86_parser_type {
+    X86_PARSER_NASM = 0,
+    X86_PARSER_TASM = 1,
+    X86_PARSER_GAS = 2
+};
+
+#define PARSER(arch) (((arch)->parser == X86_PARSER_GAS && (arch)->gas_intel_mode) ? X86_PARSER_NASM : (arch)->parser)
 
 typedef struct yasm_arch_x86 {
     yasm_arch_base arch;        /* base structure */
 
     /* What instructions/features are enabled? */
     unsigned int active_cpu;        /* active index into cpu_enables table */
     unsigned int cpu_enables_size;  /* size of cpu_enables table */
     wordptr *cpu_enables;
 
     unsigned int amd64_machine;
-    enum {
-        X86_PARSER_NASM = 0,
-        X86_PARSER_TASM = 1,
-        X86_PARSER_GAS = 2
-    } parser;
+    enum x86_parser_type parser;
     unsigned int mode_bits;
     unsigned int force_strict;
     unsigned int default_rel;
+    unsigned int gas_intel_mode;
 
     enum {
         X86_NOP_BASIC = 0,
         X86_NOP_INTEL = 1,
         X86_NOP_AMD = 2
     } nop;
 } yasm_arch_x86;
 
 /* 0-15 (low 4 bits) used for register number, stored in same data area.
  * Note 8-15 are only valid for some registers, and only in 64-bit mode.
@@ skipping 43 matching lines @@
     X86_REX_R = 2,
     X86_REX_X = 1,
     X86_REX_B = 0
 } x86_rex_bit_pos;
 
 /* Sets REX (4th bit) and 3 LS bits from register size/number.  Returns 1 if
  * impossible to fit reg into REX, otherwise returns 0.  Input parameter rexbit
  * indicates bit of REX to use if REX is needed.  Will not modify REX if not
  * in 64-bit mode or if it wasn't needed to express reg.
  */
-int yasm_x86__set_rex_from_reg(unsigned char *rex, unsigned char *drex,
-                               unsigned char *low3, uintptr_t reg,
-                               unsigned int bits, x86_rex_bit_pos rexbit);
+int yasm_x86__set_rex_from_reg(unsigned char *rex, unsigned char *low3,
+                               uintptr_t reg, unsigned int bits,
+                               x86_rex_bit_pos rexbit);
 
 /* Effective address type */
 typedef struct x86_effaddr {
     yasm_effaddr ea;            /* base structure */
 
     /* How the spare (register) bits in Mod/RM are handled:
      * Even if valid_modrm=0, the spare bits are still valid (don't overwrite!)
      * They're set in bytecode_create_insn().
      */
     unsigned char modrm;
     unsigned char valid_modrm;  /* 1 if Mod/RM byte currently valid, 0 if not */
     unsigned char need_modrm;   /* 1 if Mod/RM byte needed, 0 if not */
 
     unsigned char sib;
     unsigned char valid_sib;    /* 1 if SIB byte currently valid, 0 if not */
     unsigned char need_sib;     /* 1 if SIB byte needed, 0 if not,
                                    0xff if unknown */
-
-    unsigned char drex;         /* DREX SSE5 extension byte */
-    unsigned char need_drex;    /* 1 if DREX byte needed, 0 if not */
 } x86_effaddr;
 
 void yasm_x86__ea_init(x86_effaddr *x86_ea, unsigned int spare,
-                       unsigned int drex, unsigned int need_drex,
                        yasm_bytecode *precbc);
 
 void yasm_x86__ea_set_disponly(x86_effaddr *x86_ea);
 x86_effaddr *yasm_x86__ea_create_reg(x86_effaddr *x86_ea, unsigned long reg,
-                                     unsigned char *rex, unsigned char *drex,
-                                     unsigned int bits);
+                                     unsigned char *rex, unsigned int bits);
 x86_effaddr *yasm_x86__ea_create_imm
     (x86_effaddr *x86_ea, /*@keep@*/ yasm_expr *imm, unsigned int im_len);
 yasm_effaddr *yasm_x86__ea_create_expr(yasm_arch *arch,
                                        /*@keep@*/ yasm_expr *e);
 void yasm_x86__ea_destroy(yasm_effaddr *ea);
 void yasm_x86__ea_print(const yasm_effaddr *ea, FILE *f, int indent_level);
 
 void yasm_x86__bc_insn_opersize_override(yasm_bytecode *bc,
                                          unsigned int opersize);
 void yasm_x86__bc_insn_addrsize_override(yasm_bytecode *bc,
@@ skipping 103 matching lines @@
 int yasm_x86__intnum_tobytes
     (yasm_arch *arch, const yasm_intnum *intn, unsigned char *buf,
      size_t destsize, size_t valsize, int shift, const yasm_bytecode *bc,
      int warn);
 
 unsigned int yasm_x86__get_reg_size(uintptr_t reg);
 
 /*@only@*/ yasm_bytecode *yasm_x86__create_empty_insn(yasm_arch *arch,
                                                       unsigned long line);
 #endif