Use UnboxedInt32 and UnboxedUint32 representation for LoadIndexedInstr

runtime/vm/assembler_arm64.h

Index: runtime/vm/assembler_arm64.h
diff --git a/runtime/vm/assembler_arm64.h b/runtime/vm/assembler_arm64.h
index 0db64b9d11eba91f60478b10c068d5095f82e839..5d97185a39e9d0f6ca3b6d3b32c3402f3c3a89d4 100644
--- a/runtime/vm/assembler_arm64.h
+++ b/runtime/vm/assembler_arm64.h
@@ -840,12 +840,18 @@ class Assembler : public ValueObject {
     const Register crd = ConcreteRegister(rd);
     EmitFPIntCvtOp(FMOVRD, crd, static_cast<Register>(vn));
   }
-  void scvtfd(VRegister vd, Register rn) {
+  void scvtfdx(VRegister vd, Register rn) {
     ASSERT(rn != R31);
     ASSERT(rn != CSP);
     const Register crn = ConcreteRegister(rn);
     EmitFPIntCvtOp(SCVTFD, static_cast<Register>(vd), crn);
   }
+  void scvtfdw(VRegister vd, Register rn) {
+    ASSERT(rn != R31);
+    ASSERT(rn != CSP);
+    const Register crn = ConcreteRegister(rn);
+    EmitFPIntCvtOp(SCVTFD, static_cast<Register>(vd), crn, kWord);
+  }
   void fcvtzds(Register rd, VRegister vn) {
     ASSERT(rd != R31);
     ASSERT(rd != CSP);
@@ -1800,11 +1806,14 @@ class Assembler : public ValueObject {
     Emit(encoding);
   }
 
-  void EmitFPIntCvtOp(FPIntCvtOp op, Register rd, Register rn) {
+  void EmitFPIntCvtOp(FPIntCvtOp op, Register rd, Register rn,
+                      OperandSize sz = kDoubleWord) {
+    const int32_t sfield = (sz == kDoubleWord) ? B31 : 0;

[zra, 2014/10/09 19:21:51]

Assert that sz is either kDoubleWord or kWord since the other sizes don't make
sense.

[Cutch, 2014/10/09 20:48:22]

Done.

     const int32_t encoding =
         op |
         (static_cast<int32_t>(rd) << kRdShift) |
-        (static_cast<int32_t>(rn) << kRnShift);
+        (static_cast<int32_t>(rn) << kRnShift) |
+        sfield;
     Emit(encoding);
   }