Use UnboxedInt32 and UnboxedUint32 representation for LoadIndexedInstr

runtime/vm/simulator_arm64.cc

Index: runtime/vm/simulator_arm64.cc
diff --git a/runtime/vm/simulator_arm64.cc b/runtime/vm/simulator_arm64.cc
index dd4e611818ff29b876b3d601e3fc66a26dfc8bef..5adf5f8acec14875b55f4707b5aaa24a89b40582 100644
--- a/runtime/vm/simulator_arm64.cc
+++ b/runtime/vm/simulator_arm64.cc
@@ -2667,11 +2667,23 @@ void Simulator::DecodeFPIntCvt(Instr* instr) {
   const Register rd = instr->RdField();
   const Register rn = instr->RnField();
 
-  if ((instr->SFField() != 1) || (instr->Bit(29) != 0) ||
-      (instr->Bits(22, 2) != 1)) {
+  if ((instr->Bit(29) != 0) || (instr->Bits(22, 2) != 1)) {
     UnimplementedInstruction(instr);
     return;
   }
+  if (instr->SFField() == 0) {
+    // 32-bit.
+    if (instr->Bits(16, 5) == 2) {
+      // Format(instr, "scvtfd 'vd, 'vn");
+      const int32_t rn_val = get_wregister(rn, instr->RnMode());
+      const double vn_dbl = static_cast<double>(rn_val);
+      set_vregisterd(vd, 0, bit_cast<int64_t, double>(vn_dbl));
+      set_vregisterd(vd, 1, 0);
+    } else {
+      UnimplementedInstruction(instr);
+    }
+    return;
+  }
   if (instr->Bits(16, 5) == 2) {
     // Format(instr, "scvtfd 'vd, 'vn");

[zra, 2014/10/09 18:00:30]

Fix comment to match change in disassembler.

[Cutch, 2014/10/09 18:49:11]

Done.

     const int64_t rn_val = get_register(rn, instr->RnMode());