Use UnboxedInt32 and UnboxedUint32 representation for LoadIndexedInstr

runtime/vm/assembler_arm64.h

Index: runtime/vm/assembler_arm64.h
diff --git a/runtime/vm/assembler_arm64.h b/runtime/vm/assembler_arm64.h
index 94d66b8cd4b0a08b5910e05fa4a8bd91a92f14f6..4b8be69df7aad46639b294be87c0a825365a5fca 100644
--- a/runtime/vm/assembler_arm64.h
+++ b/runtime/vm/assembler_arm64.h
@@ -718,12 +718,20 @@ class Assembler : public ValueObject {
     const Register crd = ConcreteRegister(rd);
     EmitFPIntCvtOp(FMOVRD, crd, static_cast<Register>(vn));
   }
+  // 64-bit to double precision.
   void scvtfd(VRegister vd, Register rn) {

[zra, 2014/10/09 18:00:30]

scvtfdx to be consistent with x/w in other instructions.

[Cutch, 2014/10/09 18:49:11]

Done.

     ASSERT(rn != R31);
     ASSERT(rn != CSP);
     const Register crn = ConcreteRegister(rn);
     EmitFPIntCvtOp(SCVTFD, static_cast<Register>(vd), crn);
   }
+  // 32-bit to double precision.
+  void scvtfd32(VRegister vd, Register rn) {

[zra, 2014/10/09 18:00:30]

scvtfdw to be consistent with x/w in other instructions.

[Cutch, 2014/10/09 18:49:11]

Done.

+    ASSERT(rn != R31);
+    ASSERT(rn != CSP);
+    const Register crn = ConcreteRegister(rn);
+    EmitFPIntCvtOp(SCVTFD32, static_cast<Register>(vd), crn);

[zra, 2014/10/09 18:00:30]

Pass the size to EmitFPIntCvtOp instead of making a new opcode. Passing
kDoubleWord sets B31, passing kWord doesn't. Remove B31 from the opcodes in
FPIntCvtOp. This will make adding the 32-bit forms of the other instructions
easier if it turns out we need them, as well.

[Cutch, 2014/10/09 18:49:11]

Done.

+  }
   void fcvtzds(Register rd, VRegister vn) {
     ASSERT(rd != R31);
     ASSERT(rd != CSP);