Use UnboxedInt32 and UnboxedUint32 representation for LoadIndexedInstr

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 822 matching lines @@
     ASSERT(rn != CSP);
     const Register crn = ConcreteRegister(rn);
     EmitFPIntCvtOp(FMOVDR, static_cast<Register>(vd), crn);
   }
   void fmovrd(Register rd, VRegister vn) {
     ASSERT(rd != R31);
     ASSERT(rd != CSP);
     const Register crd = ConcreteRegister(rd);
     EmitFPIntCvtOp(FMOVRD, crd, static_cast<Register>(vn));
   }
-  void scvtfd(VRegister vd, Register rn) {
+  void scvtfdx(VRegister vd, Register rn) {
     ASSERT(rn != R31);
     ASSERT(rn != CSP);
     const Register crn = ConcreteRegister(rn);
     EmitFPIntCvtOp(SCVTFD, static_cast<Register>(vd), crn);
   }
+  void scvtfdw(VRegister vd, Register rn) {
+    ASSERT(rn != R31);
+    ASSERT(rn != CSP);
+    const Register crn = ConcreteRegister(rn);
+    EmitFPIntCvtOp(SCVTFD, static_cast<Register>(vd), crn, kWord);
+  }
   void fcvtzds(Register rd, VRegister vn) {
     ASSERT(rd != R31);
     ASSERT(rd != CSP);
     const Register crd = ConcreteRegister(rd);
     EmitFPIntCvtOp(FCVTZDS, crd, static_cast<Register>(vn));
   }
   void fmovdd(VRegister vd, VRegister vn) {
     EmitFPOneSourceOp(FMOVDD, vd, vn);
   }
   void fabsd(VRegister vd, VRegister vn) {
@@ skipping 934 matching lines @@
   }
 
   void EmitFPImm(FPImmOp op, VRegister vd, uint8_t imm8) {
     const int32_t encoding =
         op |
         (static_cast<int32_t>(vd) << kVdShift) |
         (imm8 << kImm8Shift);
     Emit(encoding);
   }
 
-  void EmitFPIntCvtOp(FPIntCvtOp op, Register rd, Register rn) {
+  void EmitFPIntCvtOp(FPIntCvtOp op, Register rd, Register rn,
+                      OperandSize sz = kDoubleWord) {
+    const int32_t sfield = (sz == kDoubleWord) ? B31 : 0;

[zra, 2014/10/09 19:21:51]

Assert that sz is either kDoubleWord or kWord since the other sizes don't make
sense.

[Cutch, 2014/10/09 20:48:22]

Done.

     const int32_t encoding =
         op |
         (static_cast<int32_t>(rd) << kRdShift) |
-        (static_cast<int32_t>(rn) << kRnShift);
+        (static_cast<int32_t>(rn) << kRnShift) |
+        sfield;
     Emit(encoding);
   }
 
   void EmitFPOneSourceOp(FPOneSourceOp op, VRegister vd, VRegister vn) {
     const int32_t encoding =
         op |
         (static_cast<int32_t>(vd) << kVdShift) |
         (static_cast<int32_t>(vn) << kVnShift);
     Emit(encoding);
   }
@@ skipping 55 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_