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Side by Side Diff: runtime/vm/assembler_arm64.h

Issue 616873003: Use UnboxedInt32 and UnboxedUint32 representation for LoadIndexedInstr (Closed) Base URL: https://dart.googlecode.com/svn/branches/bleeding_edge/dart
Patch Set: Created 6 years, 2 months ago
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1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #ifndef VM_ASSEMBLER_ARM64_H_ 5 #ifndef VM_ASSEMBLER_ARM64_H_
6 #define VM_ASSEMBLER_ARM64_H_ 6 #define VM_ASSEMBLER_ARM64_H_
7 7
8 #ifndef VM_ASSEMBLER_H_ 8 #ifndef VM_ASSEMBLER_H_
9 #error Do not include assembler_arm64.h directly; use assembler.h instead. 9 #error Do not include assembler_arm64.h directly; use assembler.h instead.
10 #endif 10 #endif
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711 ASSERT(rn != CSP); 711 ASSERT(rn != CSP);
712 const Register crn = ConcreteRegister(rn); 712 const Register crn = ConcreteRegister(rn);
713 EmitFPIntCvtOp(FMOVDR, static_cast<Register>(vd), crn); 713 EmitFPIntCvtOp(FMOVDR, static_cast<Register>(vd), crn);
714 } 714 }
715 void fmovrd(Register rd, VRegister vn) { 715 void fmovrd(Register rd, VRegister vn) {
716 ASSERT(rd != R31); 716 ASSERT(rd != R31);
717 ASSERT(rd != CSP); 717 ASSERT(rd != CSP);
718 const Register crd = ConcreteRegister(rd); 718 const Register crd = ConcreteRegister(rd);
719 EmitFPIntCvtOp(FMOVRD, crd, static_cast<Register>(vn)); 719 EmitFPIntCvtOp(FMOVRD, crd, static_cast<Register>(vn));
720 } 720 }
721 // 64-bit to double precision.
721 void scvtfd(VRegister vd, Register rn) { 722 void scvtfd(VRegister vd, Register rn) {
zra 2014/10/09 18:00:30 scvtfdx to be consistent with x/w in other instruc
Cutch 2014/10/09 18:49:11 Done.
722 ASSERT(rn != R31); 723 ASSERT(rn != R31);
723 ASSERT(rn != CSP); 724 ASSERT(rn != CSP);
724 const Register crn = ConcreteRegister(rn); 725 const Register crn = ConcreteRegister(rn);
725 EmitFPIntCvtOp(SCVTFD, static_cast<Register>(vd), crn); 726 EmitFPIntCvtOp(SCVTFD, static_cast<Register>(vd), crn);
726 } 727 }
728 // 32-bit to double precision.
729 void scvtfd32(VRegister vd, Register rn) {
zra 2014/10/09 18:00:30 scvtfdw to be consistent with x/w in other instruc
Cutch 2014/10/09 18:49:11 Done.
730 ASSERT(rn != R31);
731 ASSERT(rn != CSP);
732 const Register crn = ConcreteRegister(rn);
733 EmitFPIntCvtOp(SCVTFD32, static_cast<Register>(vd), crn);
zra 2014/10/09 18:00:30 Pass the size to EmitFPIntCvtOp instead of making
Cutch 2014/10/09 18:49:11 Done.
734 }
727 void fcvtzds(Register rd, VRegister vn) { 735 void fcvtzds(Register rd, VRegister vn) {
728 ASSERT(rd != R31); 736 ASSERT(rd != R31);
729 ASSERT(rd != CSP); 737 ASSERT(rd != CSP);
730 const Register crd = ConcreteRegister(rd); 738 const Register crd = ConcreteRegister(rd);
731 EmitFPIntCvtOp(FCVTZDS, crd, static_cast<Register>(vn)); 739 EmitFPIntCvtOp(FCVTZDS, crd, static_cast<Register>(vn));
732 } 740 }
733 void fmovdd(VRegister vd, VRegister vn) { 741 void fmovdd(VRegister vd, VRegister vn) {
734 EmitFPOneSourceOp(FMOVDD, vd, vn); 742 EmitFPOneSourceOp(FMOVDD, vd, vn);
735 } 743 }
736 void fabsd(VRegister vd, VRegister vn) { 744 void fabsd(VRegister vd, VRegister vn) {
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1705 Register value, 1713 Register value,
1706 Label* no_update); 1714 Label* no_update);
1707 1715
1708 DISALLOW_ALLOCATION(); 1716 DISALLOW_ALLOCATION();
1709 DISALLOW_COPY_AND_ASSIGN(Assembler); 1717 DISALLOW_COPY_AND_ASSIGN(Assembler);
1710 }; 1718 };
1711 1719
1712 } // namespace dart 1720 } // namespace dart
1713 1721
1714 #endif // VM_ASSEMBLER_ARM64_H_ 1722 #endif // VM_ASSEMBLER_ARM64_H_
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