Adds back arm ldrex strex.

runtime/vm/simulator_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include <setjmp.h>
 #include <stdlib.h>
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 // Only build the simulator if not compiling for real ARM hardware.
 #if !defined(HOST_ARCH_ARM)
 
 #include "vm/simulator.h"
 
 #include "vm/assembler.h"
 #include "vm/constants_arm.h"
 #include "vm/cpu.h"
 #include "vm/disassembler.h"
+#include "vm/lockers.h"
 #include "vm/native_arguments.h"
 #include "vm/stack_frame.h"
 #include "vm/thread.h"
 
 namespace dart {
 
 DEFINE_FLAG(bool, trace_sim, false, "Trace simulator execution.");
 DEFINE_FLAG(int, stop_sim_at, 0, "Address to stop simulator at.");
 
 
@@ skipping 638 matching lines @@
     // Copy the newly read line into the result.
     memmove(result + offset, line_buf, len);
     offset += len;
   }
   ASSERT(result != NULL);
   result[offset] = '\0';
   return result;
 }
 
 
-void Simulator::InitOnce() {}
+// Synchronization primitives support.
+Mutex* Simulator::exclusive_access_lock_ = NULL;
+Simulator::AddressTag Simulator::exclusive_access_state_[kNumAddressTags];
+int Simulator::next_address_tag_;
+
+
+void Simulator::SetExclusiveAccess(uword addr) {
+  Isolate* isolate = Isolate::Current();
+  ASSERT(isolate != NULL);
+  int i = 0;
+  while ((i < kNumAddressTags) &&
+         (exclusive_access_state_[i].isolate != isolate)) {
+    i++;
+  }
+  if (i == kNumAddressTags) {
+    i = next_address_tag_;
+    if (++next_address_tag_ == kNumAddressTags) next_address_tag_ = 0;
+    exclusive_access_state_[i].isolate = isolate;
+  }
+  exclusive_access_state_[i].addr = addr;
+}
+
+
+bool Simulator::HasExclusiveAccessAndOpen(uword addr) {
+  Isolate* isolate = Isolate::Current();
+  ASSERT(isolate != NULL);
+  bool result = false;
+  for (int i = 0; i < kNumAddressTags; i++) {
+    if (exclusive_access_state_[i].isolate == isolate) {
+      if (exclusive_access_state_[i].addr == addr) {
+        result = true;
+      }
+      exclusive_access_state_[i].addr = NULL;
+      continue;
+    }
+    if (exclusive_access_state_[i].addr == addr) {
+      exclusive_access_state_[i].addr = NULL;
+    }
+  }
+  return result;
+}
+
+
+void Simulator::InitOnce() {
+  // Setup exclusive access state.
+  exclusive_access_lock_ = new Mutex();
+  for (int i = 0; i < kNumAddressTags; i++) {
+    exclusive_access_state_[i].isolate = NULL;
+    exclusive_access_state_[i].addr = NULL;
+  }
+  next_address_tag_ = 0;
+}
 
 
 Simulator::Simulator() {
   // Setup simulator support first. Some of this information is needed to
   // setup the architecture state.
   // We allocate the stack here, the size is computed as the sum of
   // the size specified by the user and the buffer space needed for
   // handling stack overflow exceptions. To be safe in potential
   // stack underflows we also add some underflow buffer space.
   stack_ = new char[(Isolate::GetSpecifiedStackSize() +
@@ skipping 363 matching lines @@
 
 
 void Simulator::WriteB(uword addr, uint8_t value) {
   static StatsCounter counter_write_b("Simulated byte writes");
   counter_write_b.Increment();
   uint8_t* ptr = reinterpret_cast<uint8_t*>(addr);
   *ptr = value;
 }
 
 
+// Synchronization primitives support.
+void Simulator::ClearExclusive() {
+  // This lock is initialized in Simulator::InitOnce().
+  MutexLocker ml(exclusive_access_lock_);
+  // Set exclusive access to open state for this isolate.
+  HasExclusiveAccessAndOpen(NULL);
+}
+
+
+intptr_t Simulator::ReadExclusiveW(uword addr, Instr* instr) {
+  // This lock is initialized in Simulator::InitOnce().
+  MutexLocker ml(exclusive_access_lock_);
+  SetExclusiveAccess(addr);
+  return ReadW(addr, instr);
+}
+
+
+intptr_t Simulator::WriteExclusiveW(uword addr, intptr_t value, Instr* instr) {
+  // This lock is initialized in Simulator::InitOnce().
+  MutexLocker ml(exclusive_access_lock_);
+  bool write_allowed = HasExclusiveAccessAndOpen(addr);
+  if (write_allowed) {
+    WriteW(addr, value, instr);
+    return 0;  // Success.
+  }
+  return 1;  // Failure.
+}
+
+
+uword Simulator::CompareExchange(uword* address,
+                                 uword compare_value,
+                                 uword new_value) {
+  // This lock is initialized in Simulator::InitOnce().
+  MutexLocker ml(exclusive_access_lock_);
+  uword value = *address;
+  if (value == compare_value) {
+    *address = new_value;
+    // Same effect on exclusive access state as a successful STREX.
+    HasExclusiveAccessAndOpen(reinterpret_cast<uword>(address));
+  } else {
+    // Same effect on exclusive access state as an LDREX.
+    SetExclusiveAccess(reinterpret_cast<uword>(address));
+  }
+  return value;
+}
+
+
 // Returns the top of the stack area to enable checking for stack pointer
 // validity.
 uword Simulator::StackTop() const {
   // To be safe in potential stack underflows we leave some buffer above and
   // set the stack top.
   return reinterpret_cast<uword>(stack_) +
       (Isolate::GetSpecifiedStackSize() + Isolate::kStackSizeBuffer);
 }
 
 
@@ skipping 660 matching lines @@
               SetNZFlags(hi_res);
             }
             break;
           }
           default: {
             UnimplementedInstruction(instr);
             break;
           }
         }
       } else {
-        UnimplementedInstruction(instr);
+        if (TargetCPUFeatures::arm_version() == ARMv5TE) {
+          UnimplementedInstruction(instr);
+          return;
+        }
+        // synchronization primitives
+        Register rd = instr->RdField();
+        Register rn = instr->RnField();
+        uword addr = get_register(rn);
+        switch (instr->Bits(20, 4)) {
+          case 8: {
+            // Format(instr, "strex'cond 'rd, 'rm, ['rn]");
+            if (IsIllegalAddress(addr)) {
+              HandleIllegalAccess(addr, instr);
+            } else {
+              Register rm = instr->RmField();
+              set_register(rd, WriteExclusiveW(addr, get_register(rm), instr));
+            }
+            break;
+          }
+          case 9: {
+            // Format(instr, "ldrex'cond 'rd, ['rn]");
+            if (IsIllegalAddress(addr)) {
+              HandleIllegalAccess(addr, instr);
+            } else {
+              set_register(rd, ReadExclusiveW(addr, instr));
+            }
+            break;
+          }
+          default: {
+            UnimplementedInstruction(instr);
+            break;
+          }
+        }
       }
     } else if (instr->Bit(25) == 1) {
       // 16-bit immediate loads, msr (immediate), and hints
       switch (instr->Bits(20, 5)) {
         case 16:
         case 20: {
           if (TargetCPUFeatures::arm_version() == ARMv7) {
             uint16_t imm16 = instr->MovwField();
             Register rd = instr->RdField();
             if (instr->Bit(22) == 0) {
@@ skipping 1691 matching lines @@
 void Simulator::InstructionDecode(Instr* instr) {
   pc_modified_ = false;
   if (FLAG_trace_sim) {
     const uword start = reinterpret_cast<uword>(instr);
     const uword end = start + Instr::kInstrSize;
     Disassembler::Disassemble(start, end);
   }
   if (instr->ConditionField() == kSpecialCondition) {
     if (instr->InstructionBits() == static_cast<int32_t>(0xf57ff01f)) {
       // Format(instr, "clrex");
-      UnimplementedInstruction(instr);
+      ClearExclusive();
     } else {
       if (instr->IsSIMDDataProcessing()) {
         DecodeSIMDDataProcessing(instr);
       } else {
         UnimplementedInstruction(instr);
       }
     }
   } else if (ConditionallyExecute(instr)) {
     switch (instr->TypeField()) {
       case 0:
@@ skipping 270 matching lines @@
   set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception));
   set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace));
   buf->Longjmp();
 }
 
 }  // namespace dart
 
 #endif  // !defined(HOST_ARCH_ARM)
 
 #endif  // defined TARGET_ARCH_ARM