[turbofan] x64 lea multiplication matching

src/compiler/x64/instruction-codes-x64.h

Index: src/compiler/x64/instruction-codes-x64.h
diff --git a/src/compiler/x64/instruction-codes-x64.h b/src/compiler/x64/instruction-codes-x64.h
index 336c592aba15704f0c5ff18b0f4476465129b916..cace87fd47c7ed2209f9548ccf6e6a4c71be1f62 100644
--- a/src/compiler/x64/instruction-codes-x64.h
+++ b/src/compiler/x64/instruction-codes-x64.h
@@ -68,6 +68,8 @@ namespace compiler {
   V(X64Movq)                       \
   V(X64Movsd)                      \
   V(X64Movss)                      \
+  V(X64Lea32)                      \
+  V(X64Lea)                        \
   V(X64Push)                       \
   V(X64StoreWriteBarrier)
 
@@ -81,6 +83,7 @@ namespace compiler {
 //
 // M = memory operand
 // R = base register
+// X = base == index register
 // N = index register * N for N in {1, 2, 4, 8}
 // I = immediate displacement (int32_t)
 
@@ -91,6 +94,10 @@ namespace compiler {
   V(MR2)  /* [%r1 + %r2*2    ] */      \
   V(MR4)  /* [%r1 + %r2*4    ] */      \
   V(MR8)  /* [%r1 + %r2*8    ] */      \
+  V(MX1)  /* [%r1 + %r1*1    ] */      \

[Benedikt Meurer, 2014/09/30 04:55:04]

Why do we need these additional modes? MXn is just a special case of MRn, so
it's basically redundant or am I missing something?

[dcarney, 2014/09/30 08:03:22]

The number of operands to generated instructions are different.  I wasn't sure
if we had a better way to encode this.

[Benedikt Meurer, 2014/09/30 09:14:21]

Well, just specify the same operand twice, that does the trick.

+  V(MX2)  /* [%r1 + %r1*2    ] */      \
+  V(MX4)  /* [%r1 + %r1*4    ] */      \
+  V(MX8)  /* [%r1 + %r1*8    ] */      \
   V(MR1I) /* [%r1 + %r2*1 + K] */      \
   V(MR2I) /* [%r1 + %r2*2 + K] */      \
   V(MR4I) /* [%r1 + %r2*3 + K] */      \