[turbofan] x64 lea multiplication matching

src/compiler/x64/instruction-codes-x64.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_
 #define V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_
 
 namespace v8 {
 namespace internal {
 namespace compiler {
@@ skipping 50 matching lines @@
   V(X64Movzxbl)                    \
   V(X64Movb)                       \
   V(X64Movsxwl)                    \
   V(X64Movzxwl)                    \
   V(X64Movw)                       \
   V(X64Movl)                       \
   V(X64Movsxlq)                    \
   V(X64Movq)                       \
   V(X64Movsd)                      \
   V(X64Movss)                      \
+  V(X64Lea32)                      \
+  V(X64Lea)                        \
   V(X64Push)                       \
   V(X64StoreWriteBarrier)
 
 
 // Addressing modes represent the "shape" of inputs to an instruction.
 // Many instructions support multiple addressing modes. Addressing modes
 // are encoded into the InstructionCode of the instruction and tell the
 // code generator after register allocation which assembler method to call.
 //
 // We use the following local notation for addressing modes:
 //
 // M = memory operand
 // R = base register
+// X = base == index register
 // N = index register * N for N in {1, 2, 4, 8}
 // I = immediate displacement (int32_t)
 
 #define TARGET_ADDRESSING_MODE_LIST(V) \
   V(MR)   /* [%r1            ] */      \
   V(MRI)  /* [%r1         + K] */      \
   V(MR1)  /* [%r1 + %r2*1    ] */      \
   V(MR2)  /* [%r1 + %r2*2    ] */      \
   V(MR4)  /* [%r1 + %r2*4    ] */      \
   V(MR8)  /* [%r1 + %r2*8    ] */      \
+  V(MX1)  /* [%r1 + %r1*1    ] */      \

[Benedikt Meurer, 2014/09/30 04:55:04]

Why do we need these additional modes? MXn is just a special case of MRn, so
it's basically redundant or am I missing something?

[dcarney, 2014/09/30 08:03:22]

The number of operands to generated instructions are different.  I wasn't sure
if we had a better way to encode this.

[Benedikt Meurer, 2014/09/30 09:14:21]

Well, just specify the same operand twice, that does the trick.

+  V(MX2)  /* [%r1 + %r1*2    ] */      \
+  V(MX4)  /* [%r1 + %r1*4    ] */      \
+  V(MX8)  /* [%r1 + %r1*8    ] */      \
   V(MR1I) /* [%r1 + %r2*1 + K] */      \
   V(MR2I) /* [%r1 + %r2*2 + K] */      \
   V(MR4I) /* [%r1 + %r2*3 + K] */      \
   V(MR8I) /* [%r1 + %r2*4 + K] */      \
   V(M1)   /* [      %r2*1    ] */      \
   V(M2)   /* [      %r2*2    ] */      \
   V(M4)   /* [      %r2*4    ] */      \
   V(M8)   /* [      %r2*8    ] */      \
   V(M1I)  /* [      %r2*1 + K] */      \
   V(M2I)  /* [      %r2*2 + K] */      \
   V(M4I)  /* [      %r2*4 + K] */      \
   V(M8I)  /* [      %r2*8 + K] */
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_