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Side by Side Diff: src/x64/assembler-x64.h

Issue 615223005: [turbofan] support all shift operands on x64 (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 2 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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806 void decb(const Operand& dst); 806 void decb(const Operand& dst);
807 807
808 // Sign-extends rax into rdx:rax. 808 // Sign-extends rax into rdx:rax.
809 void cqo(); 809 void cqo();
810 // Sign-extends eax into edx:eax. 810 // Sign-extends eax into edx:eax.
811 void cdq(); 811 void cdq();
812 812
813 // Multiply rax by src, put the result in rdx:rax. 813 // Multiply rax by src, put the result in rdx:rax.
814 void mul(Register src); 814 void mul(Register src);
815 815
816 #define DECLARE_SHIFT_INSTRUCTION(instruction, subcode) \ 816 #define DECLARE_SHIFT_INSTRUCTION(instruction, subcode) \
817 void instruction##p(Register dst, Immediate imm8) { \ 817 void instruction##p(Register dst, Immediate imm8) { \
818 shift(dst, imm8, subcode, kPointerSize); \ 818 shift(dst, imm8, subcode, kPointerSize); \
819 } \ 819 } \
820 \ 820 \
821 void instruction##l(Register dst, Immediate imm8) { \ 821 void instruction##l(Register dst, Immediate imm8) { \
822 shift(dst, imm8, subcode, kInt32Size); \ 822 shift(dst, imm8, subcode, kInt32Size); \
823 } \ 823 } \
824 \ 824 \
825 void instruction##q(Register dst, Immediate imm8) { \ 825 void instruction##q(Register dst, Immediate imm8) { \
826 shift(dst, imm8, subcode, kInt64Size); \ 826 shift(dst, imm8, subcode, kInt64Size); \
827 } \ 827 } \
828 \ 828 \
829 void instruction##p_cl(Register dst) { \ 829 void instruction##p(Operand dst, Immediate imm8) { \
830 shift(dst, subcode, kPointerSize); \ 830 shift(dst, imm8, subcode, kPointerSize); \
831 } \ 831 } \
832 \ 832 \
833 void instruction##l_cl(Register dst) { \ 833 void instruction##l(Operand dst, Immediate imm8) { \
834 shift(dst, subcode, kInt32Size); \ 834 shift(dst, imm8, subcode, kInt32Size); \
835 } \ 835 } \
836 \ 836 \
837 void instruction##q_cl(Register dst) { \ 837 void instruction##q(Operand dst, Immediate imm8) { \
838 shift(dst, subcode, kInt64Size); \ 838 shift(dst, imm8, subcode, kInt64Size); \
839 } 839 } \
840 \
841 void instruction##p_cl(Register dst) { shift(dst, subcode, kPointerSize); } \
842 \
843 void instruction##l_cl(Register dst) { shift(dst, subcode, kInt32Size); } \
844 \
845 void instruction##q_cl(Register dst) { shift(dst, subcode, kInt64Size); } \
846 \
847 void instruction##p_cl(Operand dst) { shift(dst, subcode, kPointerSize); } \
848 \
849 void instruction##l_cl(Operand dst) { shift(dst, subcode, kInt32Size); } \
850 \
851 void instruction##q_cl(Operand dst) { shift(dst, subcode, kInt64Size); }
840 SHIFT_INSTRUCTION_LIST(DECLARE_SHIFT_INSTRUCTION) 852 SHIFT_INSTRUCTION_LIST(DECLARE_SHIFT_INSTRUCTION)
841 #undef DECLARE_SHIFT_INSTRUCTION 853 #undef DECLARE_SHIFT_INSTRUCTION
842 854
843 // Shifts dst:src left by cl bits, affecting only dst. 855 // Shifts dst:src left by cl bits, affecting only dst.
844 void shld(Register dst, Register src); 856 void shld(Register dst, Register src);
845 857
846 // Shifts src:dst right by cl bits, affecting only dst. 858 // Shifts src:dst right by cl bits, affecting only dst.
847 void shrd(Register dst, Register src); 859 void shrd(Register dst, Register src);
848 860
849 void store_rax(void* dst, RelocInfo::Mode mode); 861 void store_rax(void* dst, RelocInfo::Mode mode);
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1358 void immediate_arithmetic_op(byte subcode, 1370 void immediate_arithmetic_op(byte subcode,
1359 Register dst, 1371 Register dst,
1360 Immediate src, 1372 Immediate src,
1361 int size); 1373 int size);
1362 void immediate_arithmetic_op(byte subcode, 1374 void immediate_arithmetic_op(byte subcode,
1363 const Operand& dst, 1375 const Operand& dst,
1364 Immediate src, 1376 Immediate src,
1365 int size); 1377 int size);
1366 1378
1367 // Emit machine code for a shift operation. 1379 // Emit machine code for a shift operation.
1380 void shift(Operand dst, Immediate shift_amount, int subcode, int size);
1368 void shift(Register dst, Immediate shift_amount, int subcode, int size); 1381 void shift(Register dst, Immediate shift_amount, int subcode, int size);
1369 // Shift dst by cl % 64 bits. 1382 // Shift dst by cl % 64 bits.
1370 void shift(Register dst, int subcode, int size); 1383 void shift(Register dst, int subcode, int size);
1384 void shift(Operand dst, int subcode, int size);
1371 1385
1372 void emit_farith(int b1, int b2, int i); 1386 void emit_farith(int b1, int b2, int i);
1373 1387
1374 // labels 1388 // labels
1375 // void print(Label* L); 1389 // void print(Label* L);
1376 void bind_to(Label* L, int pos); 1390 void bind_to(Label* L, int pos);
1377 1391
1378 // record reloc info for current pc_ 1392 // record reloc info for current pc_
1379 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 1393 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1380 1394
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1598 private: 1612 private:
1599 Assembler* assembler_; 1613 Assembler* assembler_;
1600 #ifdef DEBUG 1614 #ifdef DEBUG
1601 int space_before_; 1615 int space_before_;
1602 #endif 1616 #endif
1603 }; 1617 };
1604 1618
1605 } } // namespace v8::internal 1619 } } // namespace v8::internal
1606 1620
1607 #endif // V8_X64_ASSEMBLER_X64_H_ 1621 #endif // V8_X64_ASSEMBLER_X64_H_
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