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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ | 5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ |
6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ | 6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 namespace compiler { | 10 namespace compiler { |
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54 V(IA32StoreWriteBarrier) | 54 V(IA32StoreWriteBarrier) |
55 | 55 |
56 | 56 |
57 // Addressing modes represent the "shape" of inputs to an instruction. | 57 // Addressing modes represent the "shape" of inputs to an instruction. |
58 // Many instructions support multiple addressing modes. Addressing modes | 58 // Many instructions support multiple addressing modes. Addressing modes |
59 // are encoded into the InstructionCode of the instruction and tell the | 59 // are encoded into the InstructionCode of the instruction and tell the |
60 // code generator after register allocation which assembler method to call. | 60 // code generator after register allocation which assembler method to call. |
61 // | 61 // |
62 // We use the following local notation for addressing modes: | 62 // We use the following local notation for addressing modes: |
63 // | 63 // |
64 // R = register | 64 // M = memory operand |
65 // O = register or stack slot | 65 // R = base register |
66 // D = double register | 66 // N = index register * N for N in {1, 2, 4, 8} |
67 // I = immediate (handle, external, int32) | 67 // I = immediate displacement (int32_t) |
68 // MR = [register] | 68 |
69 // MI = [immediate] | |
70 // MRN = [register + register * N in {1, 2, 4, 8}] | |
71 // MRI = [register + immediate] | |
72 // MRNI = [register + register * N in {1, 2, 4, 8} + immediate] | |
73 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 69 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
74 V(MI) /* [K] */ \ | 70 V(MR) /* [%r1 ] */ \ |
75 V(MR) /* [%r0] */ \ | 71 V(MRI) /* [%r1 + K] */ \ |
76 V(MRI) /* [%r0 + K] */ \ | 72 V(MR1) /* [%r1 + %r2*1 ] */ \ |
77 V(MR1I) /* [%r0 + %r1 * 1 + K] */ \ | 73 V(MR2) /* [%r1 + %r2*2 ] */ \ |
78 V(MR2I) /* [%r0 + %r1 * 2 + K] */ \ | 74 V(MR4) /* [%r1 + %r2*4 ] */ \ |
79 V(MR4I) /* [%r0 + %r1 * 4 + K] */ \ | 75 V(MR8) /* [%r1 + %r2*8 ] */ \ |
80 V(MR8I) /* [%r0 + %r1 * 8 + K] */ | 76 V(MR1I) /* [%r1 + %r2*1 + K] */ \ |
| 77 V(MR2I) /* [%r1 + %r2*2 + K] */ \ |
| 78 V(MR4I) /* [%r1 + %r2*3 + K] */ \ |
| 79 V(MR8I) /* [%r1 + %r2*4 + K] */ \ |
| 80 V(M1) /* [ %r2*1 ] */ \ |
| 81 V(M2) /* [ %r2*2 ] */ \ |
| 82 V(M4) /* [ %r2*4 ] */ \ |
| 83 V(M8) /* [ %r2*8 ] */ \ |
| 84 V(M1I) /* [ %r2*1 + K] */ \ |
| 85 V(M2I) /* [ %r2*2 + K] */ \ |
| 86 V(M4I) /* [ %r2*4 + K] */ \ |
| 87 V(M8I) /* [ %r2*8 + K] */ \ |
| 88 V(MI) /* [ K] */ |
81 | 89 |
82 } // namespace compiler | 90 } // namespace compiler |
83 } // namespace internal | 91 } // namespace internal |
84 } // namespace v8 | 92 } // namespace v8 |
85 | 93 |
86 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ | 94 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ |
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