Change some explicit type checks into using helper functions.

src/assembler_ia32.cpp

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===- subzero/src/assembler_ia32.cpp - Assembler for x86-32  -------------===//
 //
 //                        The Subzero Code Generator
 //
@@ skipping 17 matching lines @@
 const Type BrokenType = IceType_i32;
 
 class DirectCallRelocation : public AssemblerFixup {
 public:
   static DirectCallRelocation *create(Assembler *Asm, FixupKind Kind,
                                       const ConstantRelocatable *Sym) {
     return new (Asm->Allocate<DirectCallRelocation>())
         DirectCallRelocation(Kind, Sym);
   }
 
-  void Process(const MemoryRegion &region, intptr_t position) {
+  void Process(const MemoryRegion &region, intptr_t position) override {
     // Direct calls are relative to the following instruction on x86.
     int32_t pointer = region.Load<int32_t>(position);
     int32_t delta = region.start() + position + sizeof(int32_t);
     region.Store<int32_t>(position, pointer - delta);
   }
 
 private:
   DirectCallRelocation(FixupKind Kind, const ConstantRelocatable *Sym)
       : AssemblerFixup(Kind, Sym) {}
 };
@@ skipping 301 matching lines @@
 void AssemblerX86::movq(XmmRegister dst, const Address &src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
   EmitUint8(0x7E);
   EmitOperand(dst, Operand(src));
 }
 
 void AssemblerX86::addss(Type Ty, XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitUint8(Ty == IceType_f32 ? 0xF3 : 0xF2);
+  EmitUint8(isFloat32Asserting32Or64(Ty) ? 0xF3 : 0xF2);
   EmitUint8(0x0F);
   EmitUint8(0x58);
   EmitXmmRegisterOperand(dst, src);
 }
 
 void AssemblerX86::addss(Type Ty, XmmRegister dst, const Address &src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitUint8(Ty == IceType_f32 ? 0xF3 : 0xF2);
+  EmitUint8(isFloat32Asserting32Or64(Ty) ? 0xF3 : 0xF2);
   EmitUint8(0x0F);
   EmitUint8(0x58);
   EmitOperand(dst, src);
 }
 
 void AssemblerX86::subss(Type Ty, XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitUint8(Ty == IceType_f32 ? 0xF3 : 0xF2);
+  EmitUint8(isFloat32Asserting32Or64(Ty) ? 0xF3 : 0xF2);
   EmitUint8(0x0F);
   EmitUint8(0x5C);
   EmitXmmRegisterOperand(dst, src);
 }
 
 void AssemblerX86::subss(Type Ty, XmmRegister dst, const Address &src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitUint8(Ty == IceType_f32 ? 0xF3 : 0xF2);
+  EmitUint8(isFloat32Asserting32Or64(Ty) ? 0xF3 : 0xF2);
   EmitUint8(0x0F);
   EmitUint8(0x5C);
   EmitOperand(dst, src);
 }
 
 void AssemblerX86::mulss(Type Ty, XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitUint8(Ty == IceType_f32 ? 0xF3 : 0xF2);
+  EmitUint8(isFloat32Asserting32Or64(Ty) ? 0xF3 : 0xF2);
   EmitUint8(0x0F);
   EmitUint8(0x59);
   EmitXmmRegisterOperand(dst, src);
 }
 
 void AssemblerX86::mulss(Type Ty, XmmRegister dst, const Address &src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitUint8(Ty == IceType_f32 ? 0xF3 : 0xF2);
+  EmitUint8(isFloat32Asserting32Or64(Ty) ? 0xF3 : 0xF2);
   EmitUint8(0x0F);
   EmitUint8(0x59);
   EmitOperand(dst, src);
 }
 
 void AssemblerX86::divss(Type Ty, XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitUint8(Ty == IceType_f32 ? 0xF3 : 0xF2);
+  EmitUint8(isFloat32Asserting32Or64(Ty) ? 0xF3 : 0xF2);
   EmitUint8(0x0F);
   EmitUint8(0x5E);
   EmitXmmRegisterOperand(dst, src);
 }
 
 void AssemblerX86::divss(Type Ty, XmmRegister dst, const Address &src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitUint8(Ty == IceType_f32 ? 0xF3 : 0xF2);
+  EmitUint8(isFloat32Asserting32Or64(Ty) ? 0xF3 : 0xF2);
   EmitUint8(0x0F);
   EmitUint8(0x5E);
   EmitOperand(dst, src);
 }
 
 void AssemblerX86::flds(const Address &src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xD9);
   EmitOperand(0, src);
 }
@@ skipping 46 matching lines @@
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0x11);
   EmitOperand(src, dst);
 }
 
 void AssemblerX86::padd(Type Ty, XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x66);
   EmitUint8(0x0F);
-  if (Ty == IceType_i8 || Ty == IceType_i1) {
+  if (isByteSizedArithType(Ty)) {
     EmitUint8(0xFC);
   } else if (Ty == IceType_i16) {
     EmitUint8(0xFD);
   } else {
     EmitUint8(0xFE);
   }
   EmitXmmRegisterOperand(dst, src);
 }
 
 void AssemblerX86::padd(Type Ty, XmmRegister dst, const Address &src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x66);
   EmitUint8(0x0F);
-  if (Ty == IceType_i8 || Ty == IceType_i1) {
+  if (isByteSizedArithType(Ty)) {
     EmitUint8(0xFC);
   } else if (Ty == IceType_i16) {
     EmitUint8(0xFD);
   } else {
     EmitUint8(0xFE);
   }
   EmitOperand(dst, src);
 }
 
 void AssemblerX86::pand(Type /* Ty */, XmmRegister dst, XmmRegister src) {
@@ skipping 57 matching lines @@
   EmitUint8(0x66);
   EmitUint8(0x0F);
   EmitUint8(0xEB);
   EmitOperand(dst, src);
 }
 
 void AssemblerX86::psub(Type Ty, XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x66);
   EmitUint8(0x0F);
-  if (Ty == IceType_i8 || Ty == IceType_i1) {
+  if (isByteSizedArithType(Ty)) {
     EmitUint8(0xF8);
   } else if (Ty == IceType_i16) {
     EmitUint8(0xF9);
   } else {
     EmitUint8(0xFA);
   }
   EmitXmmRegisterOperand(dst, src);
 }
 
 void AssemblerX86::psub(Type Ty, XmmRegister dst, const Address &src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x66);
   EmitUint8(0x0F);
-  if (Ty == IceType_i8 || Ty == IceType_i1) {
+  if (isByteSizedArithType(Ty)) {
     EmitUint8(0xF8);
   } else if (Ty == IceType_i16) {
     EmitUint8(0xF9);
   } else {
     EmitUint8(0xFA);
   }
   EmitOperand(dst, src);
 }
 
 void AssemblerX86::pxor(Type /* Ty */, XmmRegister dst, XmmRegister src) {
@@ skipping 360 matching lines @@
 
 void AssemblerX86::movmskps(GPRRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0x50);
   EmitXmmRegisterOperand(dst, src);
 }
 
 void AssemblerX86::sqrtss(Type Ty, XmmRegister dst, const Address &src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitUint8(Ty == IceType_f32 ? 0xF3 : 0xF2);
+  EmitUint8(isFloat32Asserting32Or64(Ty) ? 0xF3 : 0xF2);
   EmitUint8(0x0F);
   EmitUint8(0x51);
   EmitOperand(dst, src);
 }
 
 void AssemblerX86::sqrtss(Type Ty, XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitUint8(Ty == IceType_f32 ? 0xF3 : 0xF2);
+  EmitUint8(isFloat32Asserting32Or64(Ty) ? 0xF3 : 0xF2);
   EmitUint8(0x0F);
   EmitUint8(0x51);
   EmitXmmRegisterOperand(dst, src);
 }
 
 void AssemblerX86::xorpd(XmmRegister dst, const Address &src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x66);
   EmitUint8(0x0F);
   EmitUint8(0x57);
@@ skipping 205 matching lines @@
     EmitUint8(0xF7);
     EmitOperand(0, Operand(reg));
     EmitImmediate(BrokenType, immediate);
   }
 }
 
 void AssemblerX86::And(Type Ty, GPRRegister dst, GPRRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedType(Ty))
     EmitUint8(0x22);
   else
     EmitUint8(0x23);
   EmitRegisterOperand(dst, src);
 }
 
 void AssemblerX86::And(Type Ty, GPRRegister dst, const Address &address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedType(Ty))
     EmitUint8(0x22);
   else
     EmitUint8(0x23);
   EmitOperand(dst, address);
 }
 
 void AssemblerX86::And(Type Ty, GPRRegister dst, const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  if (Ty == IceType_i8 || Ty == IceType_i1) {
+  if (isByteSizedType(Ty)) {
     EmitComplexI8(4, Operand(dst), imm);
     return;
   }
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
   EmitComplex(Ty, 4, Operand(dst), imm);
 }
 
 void AssemblerX86::Or(Type Ty, GPRRegister dst, GPRRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedType(Ty))
     EmitUint8(0x0A);
   else
     EmitUint8(0x0B);
   EmitRegisterOperand(dst, src);
 }
 
 void AssemblerX86::Or(Type Ty, GPRRegister dst, const Address &address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedType(Ty))
     EmitUint8(0x0A);
   else
     EmitUint8(0x0B);
   EmitOperand(dst, address);
 }
 
 void AssemblerX86::Or(Type Ty, GPRRegister dst, const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  if (Ty == IceType_i8 || Ty == IceType_i1) {
+  if (isByteSizedType(Ty)) {
     EmitComplexI8(1, Operand(dst), imm);
     return;
   }
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
   EmitComplex(Ty, 1, Operand(dst), imm);
 }
 
 void AssemblerX86::Xor(Type Ty, GPRRegister dst, GPRRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedType(Ty))
     EmitUint8(0x32);
   else
     EmitUint8(0x33);
   EmitRegisterOperand(dst, src);
 }
 
 void AssemblerX86::Xor(Type Ty, GPRRegister dst, const Address &address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedType(Ty))
     EmitUint8(0x32);
   else
     EmitUint8(0x33);
   EmitOperand(dst, address);
 }
 
 void AssemblerX86::Xor(Type Ty, GPRRegister dst, const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  if (Ty == IceType_i8 || Ty == IceType_i1) {
+  if (isByteSizedType(Ty)) {
     EmitComplexI8(6, Operand(dst), imm);
     return;
   }
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
   EmitComplex(Ty, 6, Operand(dst), imm);
 }
 
 void AssemblerX86::add(Type Ty, GPRRegister dst, GPRRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0x02);
   else
     EmitUint8(0x03);
   EmitRegisterOperand(dst, src);
 }
 
 void AssemblerX86::add(Type Ty, GPRRegister reg, const Address &address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0x02);
   else
     EmitUint8(0x03);
   EmitOperand(reg, address);
 }
 
 void AssemblerX86::add(Type Ty, GPRRegister reg, const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  if (Ty == IceType_i8 || Ty == IceType_i1) {
+  if (isByteSizedArithType(Ty)) {
     EmitComplexI8(0, Operand(reg), imm);
     return;
   }
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
   EmitComplex(Ty, 0, Operand(reg), imm);
 }
 
 void AssemblerX86::adc(Type Ty, GPRRegister dst, GPRRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0x12);
   else
     EmitUint8(0x13);
   EmitRegisterOperand(dst, src);
 }
 
 void AssemblerX86::adc(Type Ty, GPRRegister dst, const Address &address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0x12);
   else
     EmitUint8(0x13);
   EmitOperand(dst, address);
 }
 
 void AssemblerX86::adc(Type Ty, GPRRegister reg, const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  if (Ty == IceType_i8 || Ty == IceType_i1) {
+  if (isByteSizedArithType(Ty)) {
     EmitComplexI8(2, Operand(reg), imm);
     return;
   }
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
   EmitComplex(Ty, 2, Operand(reg), imm);
 }
 
 void AssemblerX86::sub(Type Ty, GPRRegister dst, GPRRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0x2A);
   else
     EmitUint8(0x2B);
   EmitRegisterOperand(dst, src);
 }
 
 void AssemblerX86::sub(Type Ty, GPRRegister reg, const Address &address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0x2A);
   else
     EmitUint8(0x2B);
   EmitOperand(reg, address);
 }
 
 void AssemblerX86::sub(Type Ty, GPRRegister reg, const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  if (Ty == IceType_i8 || Ty == IceType_i1) {
+  if (isByteSizedArithType(Ty)) {
     EmitComplexI8(5, Operand(reg), imm);
     return;
   }
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
   EmitComplex(Ty, 5, Operand(reg), imm);
 }
 
 void AssemblerX86::sbb(Type Ty, GPRRegister dst, GPRRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0x1A);
   else
     EmitUint8(0x1B);
   EmitRegisterOperand(dst, src);
 }
 
 void AssemblerX86::sbb(Type Ty, GPRRegister dst, const Address &address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0x1A);
   else
     EmitUint8(0x1B);
   EmitOperand(dst, address);
 }
 
 void AssemblerX86::sbb(Type Ty, GPRRegister reg, const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  if (Ty == IceType_i8 || Ty == IceType_i1) {
+  if (isByteSizedArithType(Ty)) {
     EmitComplexI8(3, Operand(reg), imm);
     return;
   }
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
   EmitComplex(Ty, 3, Operand(reg), imm);
 }
 
 void AssemblerX86::cbw() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandSizeOverride();
   EmitUint8(0x98);
 }
 
 void AssemblerX86::cwd() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandSizeOverride();
   EmitUint8(0x99);
 }
 
 void AssemblerX86::cdq() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x99);
 }
 
 void AssemblerX86::div(Type Ty, GPRRegister reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0xF6);
   else
     EmitUint8(0xF7);
   EmitRegisterOperand(6, reg);
 }
 
 void AssemblerX86::div(Type Ty, const Address &addr) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0xF6);
   else
     EmitUint8(0xF7);
   EmitOperand(6, addr);
 }
 
 void AssemblerX86::idiv(Type Ty, GPRRegister reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0xF6);
   else
     EmitUint8(0xF7);
   EmitRegisterOperand(7, reg);
 }
 
 void AssemblerX86::idiv(Type Ty, const Address &addr) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0xF6);
   else
     EmitUint8(0xF7);
   EmitOperand(7, addr);
 }
 
 void AssemblerX86::imull(GPRRegister dst, GPRRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xAF);
@@ skipping 23 matching lines @@
 void AssemblerX86::imull(const Address &address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF7);
   EmitOperand(5, address);
 }
 
 void AssemblerX86::mul(Type Ty, GPRRegister reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0xF6);
   else
     EmitUint8(0xF7);
   EmitRegisterOperand(4, reg);
 }
 
 void AssemblerX86::mul(Type Ty, const Address &address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0xF6);
   else
     EmitUint8(0xF7);
   EmitOperand(4, address);
 }
 
 void AssemblerX86::incl(GPRRegister reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x40 + reg);
 }
@@ skipping 92 matching lines @@
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xAD);
   EmitOperand(src, Operand(dst));
 }
 
 void AssemblerX86::neg(Type Ty, GPRRegister reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0xF6);
   else
     EmitUint8(0xF7);
   EmitRegisterOperand(3, reg);
 }
 
 void AssemblerX86::neg(Type Ty, const Address &addr) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0xF6);
   else
     EmitUint8(0xF7);
   EmitOperand(3, addr);
 }
 
 void AssemblerX86::notl(GPRRegister reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF7);
   EmitUint8(0xD0 | reg);
@@ skipping 218 matching lines @@
 void AssemblerX86::lock() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF0);
 }
 
 void AssemblerX86::cmpxchg(Type Ty, const Address &address, GPRRegister reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
   EmitUint8(0x0F);
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0xB0);
   else
     EmitUint8(0xB1);
   EmitOperand(reg, address);
 }
 
 void AssemblerX86::cmpxchg8b(const Address &address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xC7);
   EmitOperand(1, address);
 }
 
 void AssemblerX86::xadd(Type Ty, const Address &addr, GPRRegister reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
   EmitUint8(0x0F);
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0xC0);
   else
     EmitUint8(0xC1);
   EmitOperand(reg, addr);
 }
 
 void AssemblerX86::xchg(Type Ty, const Address &addr, GPRRegister reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (Ty == IceType_i16)
     EmitOperandSizeOverride();
-  if (Ty == IceType_i8 || Ty == IceType_i1)
+  if (isByteSizedArithType(Ty))
     EmitUint8(0x86);
   else
     EmitUint8(0x87);
   EmitOperand(reg, addr);
 }
 
 void AssemblerX86::Align(intptr_t alignment, intptr_t offset) {
   assert(llvm::isPowerOf2_32(alignment));
   intptr_t pos = offset + buffer_.GetPosition();
   intptr_t mod = pos & (alignment - 1);
@@ skipping 128 matching lines @@
 void AssemblerX86::EmitGenericShift(int rm, const Operand &operand,
                                     GPRRegister shifter) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   assert(shifter == RegX8632::Encoded_Reg_ecx);
   EmitUint8(0xD3);
   EmitOperand(rm, Operand(operand));
 }
 
 } // end of namespace x86
 } // end of namespace Ice