Change some explicit type checks into using helper functions.

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX8632 class, which
@@ skipping 1563 matching lines @@
       _mov(Dest, T);
       break;
     case InstArithmetic::Mul:
       // TODO: Optimize for llvm::isa<Constant>(Src1)
       // TODO: Strength-reduce multiplications by a constant,
       // particularly -1 and powers of 2.  Advanced: use lea to
       // multiply by 3, 5, 9.
       //
       // The 8-bit version of imul only allows the form "imul r/m8"
       // where T must be in eax.
-      if (Dest->getType() == IceType_i8)
+      if (isByteSizedArithType(Dest->getType()))
         _mov(T, Src0, RegX8632::Reg_eax);
       else
         _mov(T, Src0);
       _imul(T, Src1);
       _mov(Dest, T);
       break;
     case InstArithmetic::Shl:
       _mov(T, Src0);
       if (!llvm::isa<Constant>(Src1))
         Src1 = legalizeToVar(Src1, RegX8632::Reg_ecx);
@@ skipping 11 matching lines @@
       _mov(T, Src0);
       if (!llvm::isa<Constant>(Src1))
         Src1 = legalizeToVar(Src1, RegX8632::Reg_ecx);
       _sar(T, Src1);
       _mov(Dest, T);
       break;
     case InstArithmetic::Udiv:
       // div and idiv are the few arithmetic operators that do not allow
       // immediates as the operand.
       Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
-      if (Dest->getType() == IceType_i8) {
+      if (isByteSizedArithType(Dest->getType())) {
         Variable *T_ah = NULL;
         Constant *Zero = Ctx->getConstantZero(IceType_i8);
         _mov(T, Src0, RegX8632::Reg_eax);
         _mov(T_ah, Zero, RegX8632::Reg_ah);
         _div(T, Src1, T_ah);
         _mov(Dest, T);
       } else {
         Constant *Zero = Ctx->getConstantZero(IceType_i32);
         _mov(T, Src0, RegX8632::Reg_eax);
         _mov(T_edx, Zero, RegX8632::Reg_edx);
         _div(T, Src1, T_edx);
         _mov(Dest, T);
       }
       break;
     case InstArithmetic::Sdiv:
       Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
-      if (Dest->getType() == IceType_i8) {
+      if (isByteSizedArithType(Dest->getType())) {
         _mov(T, Src0, RegX8632::Reg_eax);
         _cbwdq(T, T);
         _idiv(T, Src1, T);
         _mov(Dest, T);
       } else {
         T_edx = makeReg(IceType_i32, RegX8632::Reg_edx);
         _mov(T, Src0, RegX8632::Reg_eax);
         _cbwdq(T_edx, T);
         _idiv(T, Src1, T_edx);
         _mov(Dest, T);
       }
       break;
     case InstArithmetic::Urem:
       Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
-      if (Dest->getType() == IceType_i8) {
+      if (isByteSizedArithType(Dest->getType())) {
         Variable *T_ah = NULL;
         Constant *Zero = Ctx->getConstantZero(IceType_i8);
         _mov(T, Src0, RegX8632::Reg_eax);
         _mov(T_ah, Zero, RegX8632::Reg_ah);
         _div(T_ah, Src1, T);
         _mov(Dest, T_ah);
       } else {
         Constant *Zero = Ctx->getConstantZero(IceType_i32);
         _mov(T_edx, Zero, RegX8632::Reg_edx);
         _mov(T, Src0, RegX8632::Reg_eax);
         _div(T_edx, Src1, T);
         _mov(Dest, T_edx);
       }
       break;
     case InstArithmetic::Srem:
       Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
-      if (Dest->getType() == IceType_i8) {
+      if (isByteSizedArithType(Dest->getType())) {
         Variable *T_ah = makeReg(IceType_i8, RegX8632::Reg_ah);
         _mov(T, Src0, RegX8632::Reg_eax);
         _cbwdq(T, T);
         Context.insert(InstFakeDef::create(Func, T_ah));
         _idiv(T_ah, Src1, T);
         _mov(Dest, T_ah);
       } else {
         T_edx = makeReg(IceType_i32, RegX8632::Reg_edx);
         _mov(T, Src0, RegX8632::Reg_eax);
         _cbwdq(T_edx, T);
@@ skipping 17 matching lines @@
       _mov(Dest, T);
       break;
     case InstArithmetic::Fdiv:
       _mov(T, Src0);
       _divss(T, Src1);
       _mov(Dest, T);
       break;
     case InstArithmetic::Frem: {
       const SizeT MaxSrcs = 2;
       Type Ty = Dest->getType();
-      InstCall *Call =
-          makeHelperCall(Ty == IceType_f32 ? "fmodf" : "fmod", Dest, MaxSrcs);
+      InstCall *Call = makeHelperCall(
+          isFloat32Asserting32Or64(Ty) ? "fmodf" : "fmod", Dest, MaxSrcs);
       Call->addArg(Src0);
       Call->addArg(Src1);
       return lowerCall(Call);
     } break;
     }
   }
 }
 
 void TargetX8632::lowerAssign(const InstAssign *Inst) {
   Variable *Dest = Inst->getDest();
@@ skipping 57 matching lines @@
   OperandList XmmArgs;
   OperandList StackArgs, StackArgLocations;
   uint32_t ParameterAreaSizeBytes = 0;
 
   // Classify each argument operand according to the location where the
   // argument is passed.
   for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) {
     Operand *Arg = Instr->getArg(i);
     Type Ty = Arg->getType();
     // The PNaCl ABI requires the width of arguments to be at least 32 bits.
-    assert(Ty == IceType_i32 || Ty == IceType_f32 || Ty == IceType_i64 ||
-           Ty == IceType_f64 || isVectorType(Ty));
+    assert(typeWidthInBytes(Ty) >= 4);
     if (isVectorType(Ty) && XmmArgs.size() < X86_MAX_XMM_ARGS) {
       XmmArgs.push_back(Arg);
     } else {
       StackArgs.push_back(Arg);
       if (isVectorType(Arg->getType())) {
         ParameterAreaSizeBytes = applyStackAlignment(ParameterAreaSizeBytes);
       }
       Variable *esp = Func->getTarget()->getPhysicalRegister(RegX8632::Reg_esp);
       Constant *Loc =
           Ctx->getConstantInt32(IceType_i32, ParameterAreaSizeBytes);
@@ skipping 125 matching lines @@
     } else {
       assert(Dest->getType() == IceType_i32 || Dest->getType() == IceType_i16 ||
              Dest->getType() == IceType_i8 || Dest->getType() == IceType_i1 ||
              isVectorType(Dest->getType()));
       if (isVectorType(Dest->getType())) {
         _movp(Dest, ReturnReg);
       } else {
         _mov(Dest, ReturnReg);
       }
     }
-  } else if (Dest->getType() == IceType_f32 || Dest->getType() == IceType_f64) {
+  } else if (isScalarFloatingType(Dest->getType())) {
     // Special treatment for an FP function which returns its result in
     // st(0).
     // If Dest ends up being a physical xmm register, the fstp emit code
     // will route st(0) through a temporary stack slot.
     _fstp(Dest);
     // Create a fake use of Dest in case it actually isn't used,
     // because st(0) still needs to be popped.
     Context.insert(InstFakeUse::create(Func, Dest));
   }
 }
@@ skipping 173 matching lines @@
       // Use a helper for converting floating-point values to 64-bit
       // integers.  SSE2 appears to have no way to convert from xmm
       // registers to something like the edx:eax register pair, and
       // gcc and clang both want to use x87 instructions complete with
       // temporary manipulation of the status word.  This helper is
       // not needed for x86-64.
       split64(Dest);
       const SizeT MaxSrcs = 1;
       Type SrcType = Inst->getSrc(0)->getType();
       InstCall *Call = makeHelperCall(
-          SrcType == IceType_f32 ? "cvtftosi64" : "cvtdtosi64", Dest, MaxSrcs);
+          isFloat32Asserting32Or64(SrcType) ? "cvtftosi64" : "cvtdtosi64", Dest,
+          MaxSrcs);
       // TODO: Call the correct compiler-rt helper function.
       Call->addArg(Inst->getSrc(0));
       lowerCall(Call);
     } else {
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       // t1.i32 = cvt Src0RM; t2.dest_type = t1; Dest = t2.dest_type
       Variable *T_1 = makeReg(IceType_i32);
       Variable *T_2 = makeReg(Dest->getType());
       _cvtt(T_1, Src0RM);
       _mov(T_2, T_1); // T_1 and T_2 may have different integer types
@@ skipping 10 matching lines @@
       InstCall *Call = makeHelperCall("Sz_fptoui_v4f32", Dest, MaxSrcs);
       Call->addArg(Inst->getSrc(0));
       lowerCall(Call);
     } else if (Dest->getType() == IceType_i64 ||
                Dest->getType() == IceType_i32) {
       // Use a helper for both x86-32 and x86-64.
       split64(Dest);
       const SizeT MaxSrcs = 1;
       Type DestType = Dest->getType();
       Type SrcType = Inst->getSrc(0)->getType();
-      IceString DstSubstring = (DestType == IceType_i64 ? "64" : "32");
-      IceString SrcSubstring = (SrcType == IceType_f32 ? "f" : "d");
+      IceString DstSubstring = (isInt32Asserting32Or64(DestType) ? "32" : "64");
+      IceString SrcSubstring = (isFloat32Asserting32Or64(SrcType) ? "f" : "d");
       // Possibilities are cvtftoui32, cvtdtoui32, cvtftoui64, cvtdtoui64
       IceString TargetString = "cvt" + SrcSubstring + "toui" + DstSubstring;
       // TODO: Call the correct compiler-rt helper function.
       InstCall *Call = makeHelperCall(TargetString, Dest, MaxSrcs);
       Call->addArg(Inst->getSrc(0));
       lowerCall(Call);
       return;
     } else {
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       // t1.i32 = cvt Src0RM; t2.dest_type = t1; Dest = t2.dest_type
@@ skipping 12 matching lines @@
              Inst->getSrc(0)->getType() == IceType_v4i32);
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       Variable *T = makeReg(Dest->getType());
       _cvt(T, Src0RM);
       _movp(Dest, T);
     } else if (Inst->getSrc(0)->getType() == IceType_i64) {
       // Use a helper for x86-32.
       const SizeT MaxSrcs = 1;
       Type DestType = Dest->getType();
       InstCall *Call = makeHelperCall(
-          DestType == IceType_f32 ? "cvtsi64tof" : "cvtsi64tod", Dest, MaxSrcs);
+          isFloat32Asserting32Or64(DestType) ? "cvtsi64tof" : "cvtsi64tod",

[Karl, 2014/09/29 16:20:51]

Mnior nit. This conditional and the one one for "f" or "d" appear twice. Should
it be factored into an inline function?

[jvoung (off chromium), 2014/09/29 16:57:49]

I'm inclined to leave this alone for now if that's okay. It could be good to do
that with "Call the correct compiler-rt helper function" (the TODO below).

A quick scan shows that some of the functions will have different conventions:

float __floatsisf (int i) vs double __floatsidf (int i)

sf vs df, instead of f vs d. Hopefully that is consistent for the rest of the
compiler-rt functions.

+          Dest, MaxSrcs);
       // TODO: Call the correct compiler-rt helper function.
       Call->addArg(Inst->getSrc(0));
       lowerCall(Call);
       return;
     } else {
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       // Sign-extend the operand.
       // t1.i32 = movsx Src0RM; t2 = Cvt t1.i32; Dest = t2
       Variable *T_1 = makeReg(IceType_i32);
       Variable *T_2 = makeReg(Dest->getType());
@@ skipping 13 matching lines @@
       const SizeT MaxSrcs = 1;
       InstCall *Call = makeHelperCall("Sz_uitofp_v4i32", Dest, MaxSrcs);
       Call->addArg(Src0);
       lowerCall(Call);
     } else if (Src0->getType() == IceType_i64 ||
                Src0->getType() == IceType_i32) {
       // Use a helper for x86-32 and x86-64.  Also use a helper for
       // i32 on x86-32.
       const SizeT MaxSrcs = 1;
       Type DestType = Dest->getType();
-      IceString SrcSubstring = (Src0->getType() == IceType_i64 ? "64" : "32");
-      IceString DstSubstring = (DestType == IceType_f32 ? "f" : "d");
+      IceString SrcSubstring =
+          (isInt32Asserting32Or64(Src0->getType()) ? "32" : "64");
+      IceString DstSubstring = (isFloat32Asserting32Or64(DestType) ? "f" : "d");
       // Possibilities are cvtui32tof, cvtui32tod, cvtui64tof, cvtui64tod
       IceString TargetString = "cvtui" + SrcSubstring + "to" + DstSubstring;
       // TODO: Call the correct compiler-rt helper function.
       InstCall *Call = makeHelperCall(TargetString, Dest, MaxSrcs);
       Call->addArg(Src0);
       lowerCall(Call);
       return;
     } else {
       Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
       // Zero-extend the operand.
@@ skipping 172 matching lines @@
       // is not at the lowest index.
       Constant *Mask = Ctx->getConstantInt32(IceType_i8, Index);
       T = makeReg(Ty);
       _pshufd(T, legalize(SourceVectNotLegalized, Legal_Reg | Legal_Mem), Mask);
     } else {
       T = legalizeToVar(SourceVectNotLegalized);
     }
 
     if (InVectorElementTy == IceType_i32) {
       _movd(ExtractedElementR, T);
-    } else { // Ty == Icetype_f32
+    } else { // Ty == IceType_f32
       // TODO(wala): _movss is only used here because _mov does not
       // allow a vector source and a scalar destination.  _mov should be
       // able to be used here.
       // _movss is a binary instruction, so the FakeDef is needed to
       // keep the live range analysis consistent.
       Context.insert(InstFakeDef::create(Func, ExtractedElementR));
       _movss(ExtractedElementR, T);
     }
   } else {
     assert(Ty == IceType_v16i8 || Ty == IceType_v16i1);
@@ skipping 606 matching lines @@
       Variable *T = NULL;
       _mov(T, Val);
       _rol(T, Eight);
       _mov(Dest, T);
     }
     return;
   }
   case Intrinsics::Ctpop: {
     Variable *Dest = Instr->getDest();
     Operand *Val = Instr->getArg(0);
-    InstCall *Call = makeHelperCall(Val->getType() == IceType_i64 ?
-        "__popcountdi2" : "__popcountsi2", Dest, 1);
+    InstCall *Call =
+        makeHelperCall(isInt32Asserting32Or64(Val->getType()) ? "__popcountsi2"
+                                                              : "__popcountdi2",
+                       Dest, 1);
     Call->addArg(Val);
     lowerCall(Call);
     // The popcount helpers always return 32-bit values, while the intrinsic's
     // signature matches the native POPCNT instruction and fills a 64-bit reg
     // (in 64-bit mode). Thus, clear the upper bits of the dest just in case
     // the user doesn't do that in the IR. If the user does that in the IR,
     // then this zero'ing instruction is dead and gets optimized out.
     if (Val->getType() == IceType_i64) {
       Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
@@ skipping 819 matching lines @@
 
 void TargetX8632::lowerRet(const InstRet *Inst) {
   Variable *Reg = NULL;
   if (Inst->hasRetValue()) {
     Operand *Src0 = legalize(Inst->getRetValue());
     if (Src0->getType() == IceType_i64) {
       Variable *eax = legalizeToVar(loOperand(Src0), RegX8632::Reg_eax);
       Variable *edx = legalizeToVar(hiOperand(Src0), RegX8632::Reg_edx);
       Reg = eax;
       Context.insert(InstFakeUse::create(Func, edx));
-    } else if (Src0->getType() == IceType_f32 ||
-               Src0->getType() == IceType_f64) {
+    } else if (isScalarFloatingType(Src0->getType())) {
       _fld(Src0);
     } else if (isVectorType(Src0->getType())) {
       Reg = legalizeToVar(Src0, RegX8632::Reg_xmm0);
     } else {
       _mov(Reg, Src0, RegX8632::Reg_eax);
     }
   }
   _ret(Reg);
   // Add a fake use of esp to make sure esp stays alive for the entire
   // function.  Otherwise post-call esp adjustments get dead-code
@@ skipping 368 matching lines @@
     assert(!isVectorType(From->getType()));
     bool NeedsReg = false;
     if (!(Allowed & Legal_Imm))
       // Immediate specifically not allowed
       NeedsReg = true;
     // TODO(stichnot): LEAHACK: remove Legal_Reloc once a proper
     // emitter is used.
     if (!(Allowed & Legal_Reloc) && llvm::isa<ConstantRelocatable>(From))
       // Relocatable specifically not allowed
       NeedsReg = true;
-    if (!(Allowed & Legal_Mem) &&
-        (From->getType() == IceType_f32 || From->getType() == IceType_f64))
+    if (!(Allowed & Legal_Mem) && isScalarFloatingType(From->getType()))
       // On x86, FP constants are lowered to mem operands.
       NeedsReg = true;
     if (NeedsReg) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
   if (Variable *Var = llvm::dyn_cast<Variable>(From)) {
     // Check if the variable is guaranteed a physical register.  This
     // can happen either when the variable is pre-colored or when it is
@@ skipping 268 matching lines @@
     Str << "\t.align\t" << Align << "\n";
     Str << MangledName << ":\n";
     for (SizeT i = 0; i < Size; ++i) {
       Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n";
     }
     Str << "\t.size\t" << MangledName << ", " << Size << "\n";
   }
 }
 
 } // end of namespace Ice