Make LoadIndexedInstr for Uint32List use kUnboxedUint32 representation

runtime/vm/intermediate_language_arm.cc

Index: runtime/vm/intermediate_language_arm.cc
diff --git a/runtime/vm/intermediate_language_arm.cc b/runtime/vm/intermediate_language_arm.cc
index 273cf851aaafb39bfe096a21117297193a4383b1..94481d4f1bae74e13dfebe58a2fd3648e1f277b3 100644
--- a/runtime/vm/intermediate_language_arm.cc
+++ b/runtime/vm/intermediate_language_arm.cc
@@ -1117,8 +1117,7 @@ CompileType LoadIndexedInstr::ComputeType() const {
 
     case kTypedDataInt32ArrayCid:
     case kTypedDataUint32ArrayCid:
-      return Typed32BitIsSmi() ? CompileType::FromCid(kSmiCid)
-                                : CompileType::FromCid(kMintCid);
+      return CompileType::Int();
 
     default:
       UNREACHABLE();
@@ -1142,8 +1141,9 @@ Representation LoadIndexedInstr::representation() const {
     case kTwoByteStringCid:
       return kTagged;
     case kTypedDataInt32ArrayCid:
+      return kUnboxedInt32;
     case kTypedDataUint32ArrayCid:
-      return Typed32BitIsSmi() ? kTagged : kUnboxedMint;
+      return kUnboxedUint32;
     case kTypedDataFloat32ArrayCid:
     case kTypedDataFloat64ArrayCid:
       return kUnboxedDouble;
@@ -1226,9 +1226,12 @@ LocationSummary* LoadIndexedInstr::MakeLocationSummary(Isolate* isolate,
     } else {
       locs->set_out(0, Location::RequiresFpuRegister());
     }
-  } else if (representation() == kUnboxedMint) {
-    locs->set_out(0, Location::Pair(Location::RequiresRegister(),
-                                    Location::RequiresRegister()));
+  } else if (representation() == kUnboxedUint32) {
+    ASSERT(class_id() == kTypedDataUint32ArrayCid);
+    locs->set_out(0, Location::RequiresRegister());
+  } else if (representation() == kUnboxedInt32) {
+    ASSERT(class_id() == kTypedDataInt32ArrayCid);
+    locs->set_out(0, Location::RequiresRegister());
   } else {
     ASSERT(representation() == kTagged);
     locs->set_out(0, Location::RequiresRegister());
@@ -1281,28 +1284,17 @@ void LoadIndexedInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
     return;
   }
 
-  if (representation() == kUnboxedMint) {
-    ASSERT(locs()->out(0).IsPairLocation());
-    PairLocation* result_pair = locs()->out(0).AsPairLocation();
-    const Register result1 = result_pair->At(0).reg();
-    const Register result2 = result_pair->At(1).reg();
-    switch (class_id()) {
-      case kTypedDataInt32ArrayCid:
-        // Load low word.
-        __ ldr(result1, element_address);
-        // Sign extend into high word.
-        __ SignFill(result2, result1);
-        break;
-      case kTypedDataUint32ArrayCid:
-        // Load low word.
-        __ ldr(result1, element_address);
-        // Zero high word.
-        __ eor(result2, result2, Operand(result2));
-        break;
-      default:
-        UNREACHABLE();
-        break;
-    }
+  if (representation() == kUnboxedInt32) {
+    ASSERT(class_id() == kTypedDataInt32ArrayCid);
+    const Register result = locs()->out(0).reg();
+    __ ldr(result, element_address);
+    return;
+  }
+
+  if (representation() == kUnboxedUint32) {
+    ASSERT(class_id() == kTypedDataUint32ArrayCid);
+    const Register result = locs()->out(0).reg();
+    __ ldr(result, element_address);
     return;
   }
 

[Vyacheslav Egorov (Google), 2014/09/30 16:52:51]

Maybe make code look more like on ARM64?

[Cutch, 2014/09/30 17:16:21]

Done.