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Side by Side Diff: src/IceTargetLowering.cpp

Issue 610813002: Subzero: Rewrite the pass timing infrastructure. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Bug fixes and performance improvements Created 6 years, 2 months ago
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1 //===- subzero/src/IceTargetLowering.cpp - Basic lowering implementation --===// 1 //===- subzero/src/IceTargetLowering.cpp - Basic lowering implementation --===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file implements the skeleton of the TargetLowering class, 10 // This file implements the skeleton of the TargetLowering class,
(...skipping 211 matching lines...) Expand 10 before | Expand all | Expand 10 after
222 222
223 Context.advanceCur(); 223 Context.advanceCur();
224 Context.advanceNext(); 224 Context.advanceNext();
225 } 225 }
226 226
227 // Drives register allocation, allowing all physical registers (except 227 // Drives register allocation, allowing all physical registers (except
228 // perhaps for the frame pointer) to be allocated. This set of 228 // perhaps for the frame pointer) to be allocated. This set of
229 // registers could potentially be parameterized if we want to restrict 229 // registers could potentially be parameterized if we want to restrict
230 // registers e.g. for performance testing. 230 // registers e.g. for performance testing.
231 void TargetLowering::regAlloc() { 231 void TargetLowering::regAlloc() {
232 TimerMarker T("regAlloc", Ctx);
232 LinearScan LinearScan(Func); 233 LinearScan LinearScan(Func);
233 RegSetMask RegInclude = RegSet_None; 234 RegSetMask RegInclude = RegSet_None;
234 RegSetMask RegExclude = RegSet_None; 235 RegSetMask RegExclude = RegSet_None;
235 RegInclude |= RegSet_CallerSave; 236 RegInclude |= RegSet_CallerSave;
236 RegInclude |= RegSet_CalleeSave; 237 RegInclude |= RegSet_CalleeSave;
237 if (hasFramePointer()) 238 if (hasFramePointer())
238 RegExclude |= RegSet_FramePointer; 239 RegExclude |= RegSet_FramePointer;
239 llvm::SmallBitVector RegMask = getRegisterSet(RegInclude, RegExclude); 240 llvm::SmallBitVector RegMask = getRegisterSet(RegInclude, RegExclude);
240 LinearScan.scan(RegMask); 241 LinearScan.scan(RegMask);
241 } 242 }
(...skipping 13 matching lines...) Expand all
255 if (Target == Target_ARM64) 256 if (Target == Target_ARM64)
256 return IceTargetGlobalInitARM64::create(Ctx); 257 return IceTargetGlobalInitARM64::create(Ctx);
257 #endif 258 #endif
258 llvm_unreachable("Unsupported target"); 259 llvm_unreachable("Unsupported target");
259 return NULL; 260 return NULL;
260 } 261 }
261 262
262 TargetGlobalInitLowering::~TargetGlobalInitLowering() {} 263 TargetGlobalInitLowering::~TargetGlobalInitLowering() {}
263 264
264 } // end of namespace Ice 265 } // end of namespace Ice
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