Subzero: Rewrite the pass timing infrastructure.

src/llvm2ice.cpp

 //===- subzero/src/llvm2ice.cpp - Driver for testing ----------------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines a driver that uses LLVM capabilities to parse a
@@ skipping 26 matching lines @@
         clEnumValN(Ice::IceV_Deleted, "del", "Include deleted instructions"),
         clEnumValN(Ice::IceV_InstNumbers, "instnum",
                    "Print instruction numbers"),
         clEnumValN(Ice::IceV_Preds, "pred", "Show predecessors"),
         clEnumValN(Ice::IceV_Succs, "succ", "Show successors"),
         clEnumValN(Ice::IceV_Liveness, "live", "Liveness information"),
         clEnumValN(Ice::IceV_RegManager, "rmgr", "Register manager status"),
         clEnumValN(Ice::IceV_RegOrigins, "orig", "Physical register origins"),
         clEnumValN(Ice::IceV_LinearScan, "regalloc", "Linear scan details"),
         clEnumValN(Ice::IceV_Frame, "frame", "Stack frame layout details"),
-        clEnumValN(Ice::IceV_Timing, "time", "Pass timing details"),
         clEnumValN(Ice::IceV_AddrOpt, "addropt", "Address mode optimization"),
         clEnumValN(Ice::IceV_All, "all", "Use all verbose options"),
         clEnumValN(Ice::IceV_Most, "most",
                    "Use all verbose options except 'regalloc' and 'time'"),
         clEnumValN(Ice::IceV_None, "none", "No verbosity"), clEnumValEnd));
 static cl::opt<Ice::TargetArch> TargetArch(
     "target", cl::desc("Target architecture:"), cl::init(Ice::Target_X8632),
     cl::values(
         clEnumValN(Ice::Target_X8632, "x8632", "x86-32"),
         clEnumValN(Ice::Target_X8632, "x86-32", "x86-32 (same as x8632)"),
@@ skipping 110 matching lines @@
   Flags.DisableGlobals = DisableGlobals;
   Flags.FunctionSections = FunctionSections;
   Flags.UseIntegratedAssembler = UseIntegratedAssembler;
   Flags.UseSandboxing = UseSandboxing;
   Flags.DumpStats = DumpStats;
   Flags.DefaultGlobalPrefix = DefaultGlobalPrefix;
   Flags.DefaultFunctionPrefix = DefaultFunctionPrefix;
 
   Ice::GlobalContext Ctx(Ls, Os, VMask, TargetArch, OptLevel, TestPrefix,
                          Flags);
+  static Ice::TimerIdT IDszmain = Ice::GlobalContext::getTimerID("szmain");
+  Ice::TimerMarker T(IDszmain, &Ctx);
 
   int ErrorStatus = 0;
   if (BuildOnRead) {
     Ice::PNaClTranslator Translator(&Ctx, Flags);
     Translator.translate(IRFilename);
     ErrorStatus = Translator.getErrorStatus();
   } else {
     // Parse the input LLVM IR file into a module.
     SMDiagnostic Err;
-    Ice::Timer T;
+    static Ice::TimerIdT IDparse = Ice::GlobalContext::getTimerID("parse");
+    Ice::TimerMarker T1(IDparse, &Ctx);
     Module *Mod =
         NaClParseIRFile(IRFilename, InputFileFormat, Err, getGlobalContext());
 
-    if (SubzeroTimingEnabled) {
-      std::cerr << "[Subzero timing] IR Parsing: " << T.getElapsedSec()
-                << " sec\n";
-    }
-
     if (!Mod) {
       Err.print(argv[0], errs());
       return 1;
     }
 
     Ice::Converter Converter(Mod, &Ctx, Flags);
     Converter.convertToIce();
     ErrorStatus = Converter.getErrorStatus();
   }
+  if (SubzeroTimingEnabled)
+    Ctx.dumpTimers();
   const bool FinalStats = true;
   Ctx.dumpStats("_FINAL_", FinalStats);
   return ErrorStatus;
 }