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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include "vm/globals.h" | 5 #include "vm/globals.h" |
| 6 #if defined(TARGET_ARCH_ARM) | 6 #if defined(TARGET_ARCH_ARM) |
| 7 | 7 |
| 8 #include "vm/assembler.h" | 8 #include "vm/assembler.h" |
| 9 #include "vm/cpu.h" | 9 #include "vm/cpu.h" |
| 10 #include "vm/longjump.h" | 10 #include "vm/longjump.h" |
| (...skipping 673 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 684 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | | 684 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 685 B27 | B26 | B22 | B20 | | 685 B27 | B26 | B22 | B20 | |
| 686 (static_cast<int32_t>(rt2)*B16) | | 686 (static_cast<int32_t>(rt2)*B16) | |
| 687 (static_cast<int32_t>(rt)*B12) | B11 | B9 | | 687 (static_cast<int32_t>(rt)*B12) | B11 | B9 | |
| 688 ((static_cast<int32_t>(sm) & 1)*B5) | B4 | | 688 ((static_cast<int32_t>(sm) & 1)*B5) | B4 | |
| 689 (static_cast<int32_t>(sm) >> 1); | 689 (static_cast<int32_t>(sm) >> 1); |
| 690 Emit(encoding); | 690 Emit(encoding); |
| 691 } | 691 } |
| 692 | 692 |
| 693 | 693 |
| 694 void Assembler::vmovdr(DRegister dn, int i, Register rt, Condition cond) { |
| 695 ASSERT(TargetCPUFeatures::vfp_supported()); |
| 696 ASSERT((i == 0) || (i == 1)); |
| 697 ASSERT(rt != kNoRegister); |
| 698 ASSERT(rt != SP); |
| 699 ASSERT(rt != PC); |
| 700 ASSERT(dn != kNoDRegister); |
| 701 ASSERT(cond != kNoCondition); |
| 702 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 703 B27 | B26 | B25 | |
| 704 (i*B21) | |
| 705 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | |
| 706 ((static_cast<int32_t>(dn) >> 4)*B7) | |
| 707 ((static_cast<int32_t>(dn) & 0xf)*B16) | B4; |
| 708 Emit(encoding); |
| 709 } |
| 710 |
| 711 |
| 694 void Assembler::vmovdrr(DRegister dm, Register rt, Register rt2, | 712 void Assembler::vmovdrr(DRegister dm, Register rt, Register rt2, |
| 695 Condition cond) { | 713 Condition cond) { |
| 696 ASSERT(TargetCPUFeatures::vfp_supported()); | 714 ASSERT(TargetCPUFeatures::vfp_supported()); |
| 697 ASSERT(dm != kNoDRegister); | 715 ASSERT(dm != kNoDRegister); |
| 698 ASSERT(rt != kNoRegister); | 716 ASSERT(rt != kNoRegister); |
| 699 ASSERT(rt != SP); | 717 ASSERT(rt != SP); |
| 700 ASSERT(rt != PC); | 718 ASSERT(rt != PC); |
| 701 ASSERT(rt2 != kNoRegister); | 719 ASSERT(rt2 != kNoRegister); |
| 702 ASSERT(rt2 != SP); | 720 ASSERT(rt2 != SP); |
| 703 ASSERT(rt2 != PC); | 721 ASSERT(rt2 != PC); |
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| 2447 } else if (Operand::CanHold(~value, &o)) { | 2465 } else if (Operand::CanHold(~value, &o)) { |
| 2448 mvn(rd, o, cond); | 2466 mvn(rd, o, cond); |
| 2449 } else { | 2467 } else { |
| 2450 LoadDecodableImmediate(rd, value, cond); | 2468 LoadDecodableImmediate(rd, value, cond); |
| 2451 } | 2469 } |
| 2452 } | 2470 } |
| 2453 | 2471 |
| 2454 | 2472 |
| 2455 void Assembler::LoadSImmediate(SRegister sd, float value, Condition cond) { | 2473 void Assembler::LoadSImmediate(SRegister sd, float value, Condition cond) { |
| 2456 if (!vmovs(sd, value, cond)) { | 2474 if (!vmovs(sd, value, cond)) { |
| 2475 const DRegister dd = static_cast<DRegister>(sd >> 1); |
| 2476 const int index = sd & 1; |
| 2457 LoadImmediate(IP, bit_cast<int32_t, float>(value), cond); | 2477 LoadImmediate(IP, bit_cast<int32_t, float>(value), cond); |
| 2458 vmovsr(sd, IP, cond); | 2478 vmovdr(dd, index, IP, cond); |
| 2459 } | 2479 } |
| 2460 } | 2480 } |
| 2461 | 2481 |
| 2462 | 2482 |
| 2463 void Assembler::LoadDImmediate(DRegister dd, | 2483 void Assembler::LoadDImmediate(DRegister dd, |
| 2464 double value, | 2484 double value, |
| 2465 Register scratch, | 2485 Register scratch, |
| 2466 Condition cond) { | 2486 Condition cond) { |
| 2467 ASSERT(scratch != PC); | 2487 ASSERT(scratch != PC); |
| 2468 ASSERT(scratch != IP); | 2488 ASSERT(scratch != IP); |
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| 3396 | 3416 |
| 3397 | 3417 |
| 3398 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3418 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
| 3399 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3419 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
| 3400 return fpu_reg_names[reg]; | 3420 return fpu_reg_names[reg]; |
| 3401 } | 3421 } |
| 3402 | 3422 |
| 3403 } // namespace dart | 3423 } // namespace dart |
| 3404 | 3424 |
| 3405 #endif // defined TARGET_ARCH_ARM | 3425 #endif // defined TARGET_ARCH_ARM |
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