Frees up LR on arm for use by the register allocator.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 2358 matching lines @@
   // Use a fixed size code sequence, since a function prologue may be patched
   // with this branch sequence.
   // Contrarily to BranchLinkPatchable, BranchPatchable requires an instruction
   // cache flush upon patching.
   LoadPatchableImmediate(IP, label->address());
   bx(IP);
 }
 
 
 void Assembler::BranchLink(const ExternalLabel* label) {
-  LoadImmediate(IP, label->address());  // Target address is never patched.
-  blx(IP);  // Use blx instruction so that the return branch prediction works.
+  LoadImmediate(LR, label->address());  // Target address is never patched.
+  blx(LR);  // Use blx instruction so that the return branch prediction works.
 }
 
 
 void Assembler::BranchLinkPatchable(const ExternalLabel* label) {
   // Make sure that class CallPattern is able to patch the label referred
   // to by this code sequence.
   // For added code robustness, use 'blx lr' in a patchable sequence and
   // use 'blx ip' in a non-patchable sequence (see other BranchLink flavors).
   const int32_t offset =
       Array::data_offset() + 4*AddExternalLabel(label) - kHeapObjectTag;
@@ skipping 551 matching lines @@
   // the C++ world.
   AddImmediate(SP, -frame_space);
   if (OS::ActivationFrameAlignment() > 1) {
     bic(SP, SP, Operand(OS::ActivationFrameAlignment() - 1));
   }
 }
 
 
 void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
   // Preserve volatile CPU registers.
-  EnterFrame(kDartVolatileCpuRegs | (1 << FP) | (1 << LR), 0);
+  EnterFrame(kDartVolatileCpuRegs | (1 << FP), 0);
 
   // Preserve all volatile FPU registers.
   if (TargetCPUFeatures::vfp_supported()) {
     DRegister firstv = EvenDRegisterOf(kDartFirstVolatileFpuReg);
     DRegister lastv = OddDRegisterOf(kDartLastVolatileFpuReg);
     if ((lastv - firstv + 1) >= 16) {
       DRegister mid = static_cast<DRegister>(firstv + 16);
       vstmd(DB_W, SP, mid, lastv - mid + 1);
       vstmd(DB_W, SP, firstv, 16);
     } else {
@@ skipping 24 matching lines @@
     if ((lastv - firstv + 1) >= 16) {
       DRegister mid = static_cast<DRegister>(firstv + 16);
       vldmd(IA_W, SP, firstv, 16);
       vldmd(IA_W, SP, mid, lastv - mid + 1);
     } else {
       vldmd(IA_W, SP, firstv, lastv - firstv + 1);
     }
   }
 
   // Restore volatile CPU registers.
-  LeaveFrame(kDartVolatileCpuRegs | (1 << FP) | (1 << LR));
+  LeaveFrame(kDartVolatileCpuRegs | (1 << FP));
 }
 
 
 void Assembler::CallRuntime(const RuntimeEntry& entry,
                             intptr_t argument_count) {
   entry.Call(this, argument_count);
 }
 
 
 void Assembler::EnterDartFrame(intptr_t frame_size) {
@@ skipping 386 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM