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Side by Side Diff: src/mips64/assembler-mips64-inl.h

Issue 601783002: MIPS: [turbofan] Add backend support for float32. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 2 months ago
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1 1
2 // Copyright (c) 1994-2006 Sun Microsystems Inc. 2 // Copyright (c) 1994-2006 Sun Microsystems Inc.
3 // All Rights Reserved. 3 // All Rights Reserved.
4 // 4 //
5 // Redistribution and use in source and binary forms, with or without 5 // Redistribution and use in source and binary forms, with or without
6 // modification, are permitted provided that the following conditions are 6 // modification, are permitted provided that the following conditions are
7 // met: 7 // met:
8 // 8 //
9 // - Redistributions of source code must retain the above copyright notice, 9 // - Redistributions of source code must retain the above copyright notice,
10 // this list of conditions and the following disclaimer. 10 // this list of conditions and the following disclaimer.
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92 int DoubleRegister::NumRegisters() { 92 int DoubleRegister::NumRegisters() {
93 return FPURegister::kMaxNumRegisters; 93 return FPURegister::kMaxNumRegisters;
94 } 94 }
95 95
96 96
97 int DoubleRegister::NumAllocatableRegisters() { 97 int DoubleRegister::NumAllocatableRegisters() {
98 return FPURegister::kMaxNumAllocatableRegisters; 98 return FPURegister::kMaxNumAllocatableRegisters;
99 } 99 }
100 100
101 101
102 int DoubleRegister::NumAllocatableAliasedRegisters() {
103 return NumAllocatableRegisters();
104 }
105
106
102 int FPURegister::ToAllocationIndex(FPURegister reg) { 107 int FPURegister::ToAllocationIndex(FPURegister reg) {
103 DCHECK(reg.code() % 2 == 0); 108 DCHECK(reg.code() % 2 == 0);
104 DCHECK(reg.code() / 2 < kMaxNumAllocatableRegisters); 109 DCHECK(reg.code() / 2 < kMaxNumAllocatableRegisters);
105 DCHECK(reg.is_valid()); 110 DCHECK(reg.is_valid());
106 DCHECK(!reg.is(kDoubleRegZero)); 111 DCHECK(!reg.is(kDoubleRegZero));
107 DCHECK(!reg.is(kLithiumScratchDouble)); 112 DCHECK(!reg.is(kLithiumScratchDouble));
108 return (reg.code() / 2); 113 return (reg.code() / 2);
109 } 114 }
110 115
111 116
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448 } 453 }
449 *reinterpret_cast<uint64_t*>(pc_) = x; 454 *reinterpret_cast<uint64_t*>(pc_) = x;
450 pc_ += kInstrSize * 2; 455 pc_ += kInstrSize * 2;
451 CheckTrampolinePoolQuick(); 456 CheckTrampolinePoolQuick();
452 } 457 }
453 458
454 459
455 } } // namespace v8::internal 460 } } // namespace v8::internal
456 461
457 #endif // V8_MIPS_ASSEMBLER_MIPS_INL_H_ 462 #endif // V8_MIPS_ASSEMBLER_MIPS_INL_H_
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