src/compiler/mips/instruction-codes-mips.h - Issue 601723002: MIPS: Add turbofan support for mips32.

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Issue 601723002: MIPS: Add turbofan support for mips32. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge

Patch Set: minor cleanups Created 6 years, 2 months ago

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	1 // Copyright 2014 the V8 project authors. All rights reserved.

	2 // Use of this source code is governed by a BSD-style license that can be

	3 // found in the LICENSE file.

	4

	5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_

	6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_

	7

	8 namespace v8 {

	9 namespace internal {

	10 namespace compiler {

	11

	12 // MIPS-specific opcodes that specify which assembly sequence to emit.

	13 // Most opcodes specify a single instruction.

	14 #define TARGET_ARCH_OPCODE_LIST(V) \

	15 V(MipsAdd) \

	16 V(MipsAddOvf) \

	17 V(MipsSub) \

	18 V(MipsSubOvf) \

	19 V(MipsMul) \

	20 V(MipsDiv) \

	21 V(MipsDivU) \

	22 V(MipsMod) \

	23 V(MipsModU) \

	24 V(MipsAnd) \

	25 V(MipsOr) \

	26 V(MipsXor) \

	27 V(MipsShl) \

	28 V(MipsShr) \

	29 V(MipsSar) \

	30 V(MipsRor) \

	31 V(MipsMov) \

	32 V(MipsTst) \

	33 V(MipsCmp) \

	34 V(MipsFloat64Cmp) \
	titzer 2014/09/24 15:23:32 Consider naming these opcodes as close as possible Consider naming these opcodes as close as possible to the underlying Assembler/MacroAssembler method that they end up calling. We didn't do that on arm but I think we want to clean that up in the future. Benedikt Meurer 2014/09/25 05:37:10 Yep, it's on my TODO list for ARM. Show quoted text On 2014/09/24 at 15:23:32, titzer wrote: > Consider naming these opcodes as close as possible to the underlying Assembler/MacroAssembler method that they end up calling. We didn't do that on arm but I think we want to clean that up in the future. Yep, it's on my TODO list for ARM. paul.l... 2014/09/25 17:18:39 Done. Show quoted text On 2014/09/25 05:37:10, Benedikt Meurer wrote: > On 2014/09/24 at 15:23:32, titzer wrote: > > Consider naming these opcodes as close as possible to the underlying > Assembler/MacroAssembler method that they end up calling. We didn't do that on > arm but I think we want to clean that up in the future. > > Yep, it's on my TODO list for ARM. Done.
	35 V(MipsFloat64Add) \

	36 V(MipsFloat64Sub) \

	37 V(MipsFloat64Mul) \

	38 V(MipsFloat64Div) \

	39 V(MipsFloat64Mod) \

	40 V(MipsFloat64ToInt32) \

	41 V(MipsFloat64ToUint32) \

	42 V(MipsInt32ToFloat64) \

	43 V(MipsUint32ToFloat64) \

	44 V(MipsLb) \

	45 V(MipsLbu) \

	46 V(MipsSb) \

	47 V(MipsLh) \

	48 V(MipsLhu) \

	49 V(MipsSh) \

	50 V(MipsLw) \

	51 V(MipsSw) \

	52 V(MipsLwc1) \

	53 V(MipsSwc1) \

	54 V(MipsLdc1) \

	55 V(MipsSdc1) \

	56 V(MipsPush) \

	57 V(MipsStoreWriteBarrier)

	58

	59

	60 // Addressing modes represent the "shape" of inputs to an instruction.

	61 // Many instructions support multiple addressing modes. Addressing modes

	62 // are encoded into the InstructionCode of the instruction and tell the

	63 // code generator after register allocation which assembler method to call.

	64 //

	65 // We use the following local notation for addressing modes:

	66 //

	67 // R = register

	68 // O = register or stack slot

	69 // D = double register

	70 // I = immediate (handle, external, int32)

	71 // MRI = [register + immediate]

	72 // MRR = [register + register]

	73 // TODO(plind): Add the new r6 address modes.

	74 #define TARGET_ADDRESSING_MODE_LIST(V) \

	75 V(MRI) /* [%r0 + K] */ \

	76 V(MRR) /* [%r0 + %r1] */

	77

	78

	79 } // namespace compiler

	80 } // namespace internal

	81 } // namespace v8

	82

	83 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_

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