OLD | NEW |
(Empty) | |
| 1 // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. |
| 4 |
| 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
| 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
| 7 |
| 8 namespace v8 { |
| 9 namespace internal { |
| 10 namespace compiler { |
| 11 |
| 12 // MIPS-specific opcodes that specify which assembly sequence to emit. |
| 13 // Most opcodes specify a single instruction. |
| 14 #define TARGET_ARCH_OPCODE_LIST(V) \ |
| 15 V(MipsAdd) \ |
| 16 V(MipsAddOvf) \ |
| 17 V(MipsSub) \ |
| 18 V(MipsSubOvf) \ |
| 19 V(MipsMul) \ |
| 20 V(MipsDiv) \ |
| 21 V(MipsDivU) \ |
| 22 V(MipsMod) \ |
| 23 V(MipsModU) \ |
| 24 V(MipsAnd) \ |
| 25 V(MipsOr) \ |
| 26 V(MipsXor) \ |
| 27 V(MipsShl) \ |
| 28 V(MipsShr) \ |
| 29 V(MipsSar) \ |
| 30 V(MipsRor) \ |
| 31 V(MipsMov) \ |
| 32 V(MipsTst) \ |
| 33 V(MipsCmp) \ |
| 34 V(MipsCmpD) \ |
| 35 V(MipsAddD) \ |
| 36 V(MipsSubD) \ |
| 37 V(MipsMulD) \ |
| 38 V(MipsDivD) \ |
| 39 V(MipsModD) \ |
| 40 V(MipsSqrtD) \ |
| 41 V(MipsCvtSD) \ |
| 42 V(MipsCvtDS) \ |
| 43 V(MipsTruncWD) \ |
| 44 V(MipsTruncUwD) \ |
| 45 V(MipsCvtDW) \ |
| 46 V(MipsCvtDUw) \ |
| 47 V(MipsLb) \ |
| 48 V(MipsLbu) \ |
| 49 V(MipsSb) \ |
| 50 V(MipsLh) \ |
| 51 V(MipsLhu) \ |
| 52 V(MipsSh) \ |
| 53 V(MipsLw) \ |
| 54 V(MipsSw) \ |
| 55 V(MipsLwc1) \ |
| 56 V(MipsSwc1) \ |
| 57 V(MipsLdc1) \ |
| 58 V(MipsSdc1) \ |
| 59 V(MipsPush) \ |
| 60 V(MipsStoreWriteBarrier) |
| 61 |
| 62 |
| 63 // Addressing modes represent the "shape" of inputs to an instruction. |
| 64 // Many instructions support multiple addressing modes. Addressing modes |
| 65 // are encoded into the InstructionCode of the instruction and tell the |
| 66 // code generator after register allocation which assembler method to call. |
| 67 // |
| 68 // We use the following local notation for addressing modes: |
| 69 // |
| 70 // R = register |
| 71 // O = register or stack slot |
| 72 // D = double register |
| 73 // I = immediate (handle, external, int32) |
| 74 // MRI = [register + immediate] |
| 75 // MRR = [register + register] |
| 76 // TODO(plind): Add the new r6 address modes. |
| 77 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
| 78 V(MRI) /* [%r0 + K] */ \ |
| 79 V(MRR) /* [%r0 + %r1] */ |
| 80 |
| 81 |
| 82 } // namespace compiler |
| 83 } // namespace internal |
| 84 } // namespace v8 |
| 85 |
| 86 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
OLD | NEW |