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Unified Diff: test/cctest/test-disasm-ia32.cc

Issue 60093005: Introduce addps/subps/mulps/divps for IA32/X64 (Closed) Base URL: git://github.com/v8/v8.git@master
Patch Set: Put all SSE1 instruction after SSE2 flag Created 7 years, 1 month ago
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Index: test/cctest/test-disasm-ia32.cc
diff --git a/test/cctest/test-disasm-ia32.cc b/test/cctest/test-disasm-ia32.cc
index 7f9a6332ac1d6cd6722a94c1ac78c97de6a3c585..2b4c82f2b12953df87b28e5235bebe2639965353 100644
--- a/test/cctest/test-disasm-ia32.cc
+++ b/test/cctest/test-disasm-ia32.cc
@@ -349,6 +349,34 @@ TEST(DisasmIa320) {
__ fcompp();
__ fwait();
__ nop();
+
+ // SSE instruction
+ {
+ if (CpuFeatures::IsSupported(SSE2)) {
+ CpuFeatureScope fscope(&assm, SSE2);
+ // Move operation
+ __ movaps(xmm0, xmm1);
+ __ shufps(xmm0, xmm0, 0x0);
+
+ // logic operation
+ __ andps(xmm0, xmm1);
+ __ andps(xmm0, Operand(ebx, ecx, times_4, 10000));
+ __ orps(xmm0, xmm1);
+ __ orps(xmm0, Operand(ebx, ecx, times_4, 10000));
+ __ xorps(xmm0, xmm1);
+ __ xorps(xmm0, Operand(ebx, ecx, times_4, 10000));
+
+ // Arithmetic operation
+ __ addps(xmm1, xmm0);
+ __ addps(xmm1, Operand(ebx, ecx, times_4, 10000));
+ __ subps(xmm1, xmm0);
+ __ subps(xmm1, Operand(ebx, ecx, times_4, 10000));
+ __ mulps(xmm1, xmm0);
+ __ mulps(xmm1, Operand(ebx, ecx, times_4, 10000));
+ __ divps(xmm1, xmm0);
+ __ divps(xmm1, Operand(ebx, ecx, times_4, 10000));
+ }
+ }
{
if (CpuFeatures::IsSupported(SSE2)) {
CpuFeatureScope fscope(&assm, SSE2);
@@ -356,7 +384,6 @@ TEST(DisasmIa320) {
__ cvtsi2sd(xmm1, Operand(ebx, ecx, times_4, 10000));
__ movsd(xmm1, Operand(ebx, ecx, times_4, 10000));
__ movsd(Operand(ebx, ecx, times_4, 10000), xmm1);
- __ movaps(xmm0, xmm1);
// 128 bit move instructions.
__ movdqa(xmm0, Operand(ebx, ecx, times_4, 10000));
__ movdqa(Operand(ebx, ecx, times_4, 10000), xmm0);
@@ -370,8 +397,6 @@ TEST(DisasmIa320) {
__ ucomisd(xmm0, xmm1);
__ cmpltsd(xmm0, xmm1);
- __ andps(xmm0, xmm1);
- __ orps(xmm0, xmm1);
__ andpd(xmm0, xmm1);
__ psllq(xmm0, 17);
__ psllq(xmm0, xmm1);
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