Introduce addps/subps/mulps/divps for IA32/X64

test/cctest/test-disasm-x64.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 72 matching lines @@
   __ and_(rdx, Immediate(3));
   __ and_(rdx, Operand(rsp, 4));
   __ cmpq(rdx, Immediate(3));
   __ cmpq(rdx, Operand(rsp, 4));
   __ cmpq(Operand(rbp, rcx, times_4, 0), Immediate(1000));
   __ cmpb(rbx, Operand(rbp, rcx, times_2, 0));
   __ cmpb(Operand(rbp, rcx, times_2, 0), rbx);
   __ or_(rdx, Immediate(3));
   __ xor_(rdx, Immediate(3));
   __ nop();
-  {
-    CHECK(CpuFeatures::IsSupported(CPUID));
-    CpuFeatures::Scope fscope(CPUID);
-    __ cpuid();
-  }
+  __ cpuid();
   __ movsxbq(rdx, Operand(rcx, 0));
   __ movsxwq(rdx, Operand(rcx, 0));
   __ movzxbl(rdx, Operand(rcx, 0));
   __ movzxwl(rdx, Operand(rcx, 0));
   __ movzxbq(rdx, Operand(rcx, 0));
   __ movzxwq(rdx, Operand(rcx, 0));
 
   __ nop();
   __ imul(rdx, rcx);
   __ shld(rdx, rcx);
@@ skipping 223 matching lines @@
   __ faddp(3);
   __ fsubp(3);
   __ fmulp(3);
   __ fdivp(3);
   __ fcompp();
   __ fwait();
   __ nop();
 
   // SSE instruction
   {
+    // Move operation
     __ cvttss2si(rdx, Operand(rbx, rcx, times_4, 10000));
     __ cvttss2si(rdx, xmm1);
     __ movaps(xmm0, xmm1);
 
+    // logic operation
     __ andps(xmm0, xmm1);
+    __ andps(xmm0, Operand(rbx, rcx, times_4, 10000));
     __ orps(xmm0, xmm1);
+    __ ordps(xmm0, Operand(rbx, rcx, times_4, 10000));
     __ xorps(xmm0, xmm1);
+    __ xordps(xmm0, Operand(rbx, rcx, times_4, 10000));
+
+    // Arithmetic operation
+    __ addps(xmm1, xmm0);
+    __ addps(xmm1, Operand(rbx, rcx, times_4, 10000));
+    __ subps(xmm1, xmm0);
+    __ subps(xmm1, Operand(rbx, rcx, times_4, 10000));
+    __ mulps(xmm1, xmm0);
+    __ mulps(xmm1, Operand(rbx, ecx, times_4, 10000));
+    __ divps(xmm1, xmm0);
+    __ divps(xmm1, Operand(rbx, rcx, times_4, 10000));
   }
   // SSE 2 instructions
   {
     __ cvttsd2si(rdx, Operand(rbx, rcx, times_4, 10000));
     __ cvttsd2si(rdx, xmm1);
     __ cvttsd2siq(rdx, xmm1);
     __ movsd(xmm1, Operand(rbx, rcx, times_4, 10000));
     __ movsd(Operand(rbx, rcx, times_4, 10000), xmm1);
     // 128 bit move instructions.
     __ movdqa(xmm0, Operand(rbx, rcx, times_4, 10000));
@@ skipping 51 matching lines @@
   CHECK(code->IsCode());
 #ifdef OBJECT_PRINT
   Code::cast(code)->Print();
   byte* begin = Code::cast(code)->instruction_start();
   byte* end = begin + Code::cast(code)->instruction_size();
   disasm::Disassembler::Disassemble(stdout, begin, end);
 #endif
 }
 
 #undef __