Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(244)

Side by Side Diff: test/cctest/test-assembler-ia32.cc

Issue 60093005: Introduce addps/subps/mulps/divps for IA32/X64 (Closed) Base URL: git://github.com/v8/v8.git@master
Patch Set: Put all SSE1 instruction after SSE2 flag Created 7 years, 1 month ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/x64/disasm-x64.cc ('k') | test/cctest/test-assembler-x64.cc » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 581 matching lines...) Expand 10 before | Expand all | Expand 10 after
592 #endif 592 #endif
593 593
594 F4 f = FUNCTION_CAST<F4>(Code::cast(code)->entry()); 594 F4 f = FUNCTION_CAST<F4>(Code::cast(code)->entry());
595 uint64_t value1 = V8_2PART_UINT64_C(0x12345678, 87654321); 595 uint64_t value1 = V8_2PART_UINT64_C(0x12345678, 87654321);
596 CHECK_EQ(0x12345678, f(uint64_to_double(value1))); 596 CHECK_EQ(0x12345678, f(uint64_to_double(value1)));
597 uint64_t value2 = V8_2PART_UINT64_C(0x87654321, 12345678); 597 uint64_t value2 = V8_2PART_UINT64_C(0x87654321, 12345678);
598 CHECK_EQ(0x87654321, f(uint64_to_double(value2))); 598 CHECK_EQ(0x87654321, f(uint64_to_double(value2)));
599 } 599 }
600 600
601 601
602 typedef int (*F8)(float x, float y);
603 TEST(AssemblerIa32SSE) {
604 CcTest::InitializeVM();
605 if (!CpuFeatures::IsSupported(SSE2)) return;
606
607 Isolate* isolate = reinterpret_cast<Isolate*>(CcTest::isolate());
608 HandleScope scope(isolate);
609 v8::internal::byte buffer[256];
610 MacroAssembler assm(isolate, buffer, sizeof buffer);
611 {
612 CpuFeatureScope fscope(&assm, SSE2);
613 __ movss(xmm0, Operand(esp, kPointerSize));
614 __ movss(xmm1, Operand(esp, 2 * kPointerSize));
615 __ shufps(xmm0, xmm0, 0x0);
616 __ shufps(xmm1, xmm1, 0x0);
617 __ movaps(xmm2, xmm1);
618 __ addps(xmm2, xmm0);
619 __ mulps(xmm2, xmm1);
620 __ subps(xmm2, xmm0);
621 __ divps(xmm2, xmm1);
622 __ cvttss2si(eax, xmm2);
623 __ ret(0);
624 }
625
626 CodeDesc desc;
627 assm.GetCode(&desc);
628 Code* code = Code::cast(isolate->heap()->CreateCode(
629 desc,
630 Code::ComputeFlags(Code::STUB),
631 Handle<Code>())->ToObjectChecked());
632 CHECK(code->IsCode());
633 #ifdef OBJECT_PRINT
634 Code::cast(code)->Print();
635 #endif
636
637 F8 f = FUNCTION_CAST<F8>(Code::cast(code)->entry());
638 CHECK_EQ(2, f(1.0, 2.0));
639 }
640
641
602 #undef __ 642 #undef __
OLDNEW
« no previous file with comments | « src/x64/disasm-x64.cc ('k') | test/cctest/test-assembler-x64.cc » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698