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Issue 60093005: Introduce addps/subps/mulps/divps for IA32/X64 (Closed) Base URL: git://github.com/v8/v8.git@master
Patch Set: Put all SSE1 instruction after SSE2 flag Created 7 years, 1 month ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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1253 // CPUID 1253 // CPUID
1254 AppendToBuffer("%s", mnemonic); 1254 AppendToBuffer("%s", mnemonic);
1255 1255
1256 } else if ((opcode & 0xF0) == 0x40) { 1256 } else if ((opcode & 0xF0) == 0x40) {
1257 // CMOVcc: conditional move. 1257 // CMOVcc: conditional move.
1258 int condition = opcode & 0x0F; 1258 int condition = opcode & 0x0F;
1259 const InstructionDesc& idesc = cmov_instructions[condition]; 1259 const InstructionDesc& idesc = cmov_instructions[condition];
1260 byte_size_operand_ = idesc.byte_size_operation; 1260 byte_size_operand_ = idesc.byte_size_operation;
1261 current += PrintOperands(idesc.mnem, idesc.op_order_, current); 1261 current += PrintOperands(idesc.mnem, idesc.op_order_, current);
1262 1262
1263 } else if (opcode == 0x54) { 1263 } else if (opcode >= 0x53 && opcode <= 0x5F) {
1264 // andps xmm, xmm/m128 1264 const char* const pseudo_op[] = {
1265 "rcpps",
1266 "andps",
1267 "andnps",
1268 "orps",
1269 "xorps",
1270 "addps",
1271 "mulps",
1272 "cvtps2pd",
1273 "cvtdq2ps",
1274 "subps",
1275 "minps",
1276 "divps",
1277 "maxps",
1278 };
1265 int mod, regop, rm; 1279 int mod, regop, rm;
1266 get_modrm(*current, &mod, &regop, &rm); 1280 get_modrm(*current, &mod, &regop, &rm);
1267 AppendToBuffer("andps %s,", NameOfXMMRegister(regop)); 1281 AppendToBuffer("%s %s,",
1282 pseudo_op[opcode - 0x53],
1283 NameOfXMMRegister(regop));
1268 current += PrintRightXMMOperand(current); 1284 current += PrintRightXMMOperand(current);
1269 1285
1270 } else if (opcode == 0x56) { 1286 } else if (opcode == 0xC6) {
1271 // orps xmm, xmm/m128 1287 // shufps xmm, xmm/m128, imm8
1272 int mod, regop, rm; 1288 int mod, regop, rm;
1273 get_modrm(*current, &mod, &regop, &rm); 1289 get_modrm(*current, &mod, &regop, &rm);
1274 AppendToBuffer("orps %s,", NameOfXMMRegister(regop)); 1290 AppendToBuffer("shufps %s, ", NameOfXMMRegister(regop));
1275 current += PrintRightXMMOperand(current); 1291 current += PrintRightXMMOperand(current);
1276 1292 AppendToBuffer(", %d", (*current) & 3);
1277 } else if (opcode == 0x57) { 1293 current += 1;
1278 // xorps xmm, xmm/m128
1279 int mod, regop, rm;
1280 get_modrm(*current, &mod, &regop, &rm);
1281 AppendToBuffer("xorps %s,", NameOfXMMRegister(regop));
1282 current += PrintRightXMMOperand(current);
1283 1294
1284 } else if (opcode == 0x50) { 1295 } else if (opcode == 0x50) {
1285 // movmskps reg, xmm 1296 // movmskps reg, xmm
1286 int mod, regop, rm; 1297 int mod, regop, rm;
1287 get_modrm(*current, &mod, &regop, &rm); 1298 get_modrm(*current, &mod, &regop, &rm);
1288 AppendToBuffer("movmskps %s,", NameOfCPURegister(regop)); 1299 AppendToBuffer("movmskps %s,", NameOfCPURegister(regop));
1289 current += PrintRightXMMOperand(current); 1300 current += PrintRightXMMOperand(current);
1290 1301
1291 } else if ((opcode & 0xF0) == 0x80) { 1302 } else if ((opcode & 0xF0) == 0x80) {
1292 // Jcc: Conditional jump (branch). 1303 // Jcc: Conditional jump (branch).
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1905 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) { 1916 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) {
1906 fprintf(f, " "); 1917 fprintf(f, " ");
1907 } 1918 }
1908 fprintf(f, " %s\n", buffer.start()); 1919 fprintf(f, " %s\n", buffer.start());
1909 } 1920 }
1910 } 1921 }
1911 1922
1912 } // namespace disasm 1923 } // namespace disasm
1913 1924
1914 #endif // V8_TARGET_ARCH_X64 1925 #endif // V8_TARGET_ARCH_X64
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