| OLD | NEW |
| 1 ; This is a regression test that idiv and div operands are legalized | 1 ; This is a regression test that idiv and div operands are legalized |
| 2 ; (they cannot be constants and can only be reg/mem for x86). | 2 ; (they cannot be constants and can only be reg/mem for x86). |
| 3 | 3 |
| 4 ; RUN: %llvm2ice -O2 --verbose none %s \ | 4 ; RUN: %p2i -i %s --args -O2 --verbose none \ |
| 5 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \ | 5 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \ |
| 6 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s | 6 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s |
| 7 ; RUN: %llvm2ice -Om1 --verbose none %s \ | 7 ; RUN: %p2i -i %s --args -Om1 --verbose none \ |
| 8 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \ | 8 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \ |
| 9 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s | 9 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s |
| 10 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s | 10 ; RUN: %p2i -i %s --args --verbose none | FileCheck --check-prefix=ERRORS %s |
| 11 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s | 11 ; RUN: %p2i -i %s --insts | %szdiff %s | FileCheck --check-prefix=DUMP %s |
| 12 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \ | |
| 13 ; RUN: | FileCheck --check-prefix=DUMP %s | |
| 14 | 12 |
| 15 define i32 @Sdiv_const8_b(i8 %a) { | 13 define i32 @Sdiv_const8_b(i8 %a) { |
| 16 ; CHECK-LABEL: Sdiv_const8_b | 14 ; CHECK-LABEL: Sdiv_const8_b |
| 17 entry: | 15 entry: |
| 18 %div = sdiv i8 %a, 12 | 16 %div = sdiv i8 %a, 12 |
| 19 ; CHECK: mov {{.*}}, 12 | 17 ; CHECK: mov {{.*}}, 12 |
| 20 ; CHECK-NOT: idiv 12 | 18 ; CHECK-NOT: idiv 12 |
| 21 %div_ext = sext i8 %div to i32 | 19 %div_ext = sext i8 %div to i32 |
| 22 ret i32 %div_ext | 20 ret i32 %div_ext |
| 23 } | 21 } |
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| 63 ; CHECK-LABEL: Urem_const_b | 61 ; CHECK-LABEL: Urem_const_b |
| 64 entry: | 62 entry: |
| 65 %rem = urem i32 %a, 4567 | 63 %rem = urem i32 %a, 4567 |
| 66 ; CHECK: mov {{.*}}, 4567 | 64 ; CHECK: mov {{.*}}, 4567 |
| 67 ; CHECK-NOT: div 4567 | 65 ; CHECK-NOT: div 4567 |
| 68 ret i32 %rem | 66 ret i32 %rem |
| 69 } | 67 } |
| 70 | 68 |
| 71 ; ERRORS-NOT: ICE translation error | 69 ; ERRORS-NOT: ICE translation error |
| 72 ; DUMP-NOT: SZ | 70 ; DUMP-NOT: SZ |
| OLD | NEW |